A Learned Performance Model With Transfer Learning Across GPUs on Tensorized Instructions

IF 5.6 2区 计算机科学 Q1 COMPUTER SCIENCE, THEORY & METHODS
Yang Bai;Mingjun Li;Wendong Xu;Bei Yu
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Abstract

The training and inference efficiency of ever-larger deep neural networks highly rely on the performance of tensor operators on specific hardware accelerators. Therefore, a performance tuning framework with tensorized instruction compilation for automatic tensor generation is necessary for efficient deployment. These novel tensorized instruction, along with the emerging machine learning models, bring tremendous engineering challenges in compilation-based methods. They suffer from a large design space exploration with rough measurement accuracy and poor transferability among specialized instructions with certain hardware constraints. This paper presents a novel performance model for automatic code optimization with tensorized instruction. Central to the performance model is the assignment feature that not only clearly specifies the behaviour of instruction with computation and data movement abstraction, but also formally defines the matching problem from algorithm to tensorized instructions. Meanwhile, a simple yet efficient design with attention-inspired modules to accurately predict the performance of optimized tensor program by capturing global and long-range dependencies within a complete scheduling space. Compared with state-of-the-arts, our performance model can predict the optimal implementation of code configurations with tensorized instruction to reduce inference latency and search time by up to 1.21× and 3.41× on modern DNN benchmarks. Furthermore, with pre-trained parameters, our performance can quickly adapt to different workloads and platforms on tensorized instruction via transfer learning.
基于张化指令的gpu迁移学习性能学习模型
越来越大的深度神经网络的训练和推理效率高度依赖于张量算子在特定硬件加速器上的性能。因此,为实现张量的自动生成,需要一个具有张量指令编译的性能调优框架。这些新颖的张紧指令,以及新兴的机器学习模型,给基于编译的方法带来了巨大的工程挑战。它们的设计空间探索大,测量精度粗糙,并且在特定硬件约束下的专用指令之间的可移植性差。提出了一种新的基于张张指令的代码自动优化性能模型。性能模型的核心是赋值特征,它不仅通过计算和数据移动抽象清楚地指定指令的行为,而且还正式定义了从算法到张紧指令的匹配问题。同时,一个简单而高效的设计与注意力启发模块,以准确预测优化张量程序的性能,通过捕获全局和远程依赖关系在一个完整的调度空间。与最先进的性能模型相比,我们的性能模型可以预测具有张拉指令的代码配置的最佳实现,在现代DNN基准测试中,可以将推理延迟和搜索时间分别减少1.21倍和3.41倍。此外,通过预训练参数,我们的性能可以通过迁移学习快速适应张化指令的不同工作负载和平台。
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来源期刊
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems 工程技术-工程:电子与电气
CiteScore
11.00
自引率
9.40%
发文量
281
审稿时长
5.6 months
期刊介绍: IEEE Transactions on Parallel and Distributed Systems (TPDS) is published monthly. It publishes a range of papers, comments on previously published papers, and survey articles that deal with the parallel and distributed systems research areas of current importance to our readers. Particular areas of interest include, but are not limited to: a) Parallel and distributed algorithms, focusing on topics such as: models of computation; numerical, combinatorial, and data-intensive parallel algorithms, scalability of algorithms and data structures for parallel and distributed systems, communication and synchronization protocols, network algorithms, scheduling, and load balancing. b) Applications of parallel and distributed computing, including computational and data-enabled science and engineering, big data applications, parallel crowd sourcing, large-scale social network analysis, management of big data, cloud and grid computing, scientific and biomedical applications, mobile computing, and cyber-physical systems. c) Parallel and distributed architectures, including architectures for instruction-level and thread-level parallelism; design, analysis, implementation, fault resilience and performance measurements of multiple-processor systems; multicore processors, heterogeneous many-core systems; petascale and exascale systems designs; novel big data architectures; special purpose architectures, including graphics processors, signal processors, network processors, media accelerators, and other special purpose processors and accelerators; impact of technology on architecture; network and interconnect architectures; parallel I/O and storage systems; architecture of the memory hierarchy; power-efficient and green computing architectures; dependable architectures; and performance modeling and evaluation. d) Parallel and distributed software, including parallel and multicore programming languages and compilers, runtime systems, operating systems, Internet computing and web services, resource management including green computing, middleware for grids, clouds, and data centers, libraries, performance modeling and evaluation, parallel programming paradigms, and programming environments and tools.
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