An efficient machine learning-enhanced DTCO framework for low-power and high-performance circuit design

Abstract

The standard design technology co-optimization (DTCO) involves frequent interactions between circuit design and process manufacturing, which requires several months. To assist designers in establishing a bridge between device parameters and circuit metrics efficiently, and provide guidance for parameter optimization in the early stages of circuit design. In this paper, we propose an efficient machine learning (ML)-enhanced DTCO framework. This framework achieves the co-optimization of device parameters and circuit metrics. We select the gate metal work function (WF) as the parameter to validate the effectiveness of our framework. And the ridge regression approach is used to bypass TCAD simulation, compact model extraction and cell library characterization. We reduces time consumption by at least 92% compared to traditional DTCO framework, while ensuring that errors of delay, internal power consumption and leakage power below 4 ps, 0.035 ​mJ, and 0.4 μW, respectively. By adjusting the WF, we achieved a better balance between circuit delay and power consumption. This work contributes to designers exploring a broader design space and achieving a efficient DTCO flow.