A 1st-Order NS-SAR⋅ADC With DCMS Switching Scheme for Smart Consumer Electronics Device

Abstract

A novel Dual-Capacitor Merge-and-Split (DCMS) capacitor switching scheme is proposed for a Noise-Shaping (NS) Successive-Approximation-Register Analog-to-Digital-Converter (SAR ADC) for smart consumer electronics device. In comparison to the $V_{\mathrm { cm}}$ -based method, the proposed DCMS scheme significantly decreases the average switching energy by 93.7%, while optimizing integral and differential non-linearity by factors of $\surd 3$ / $4\times $ and $\surd 1$ / $2\times $ , respectively. By employing only $V_{\mathrm { cm}}$ reference, the DCMS scheme can avoid the $V_{ref}$ generation circuit and mismatch between the $V_{ref}$ and $V_{\mathrm { cm}}$ compared to the tri-level or multiple-level switching schemes. Moreover, it maintains a stable common-mode output voltage, simplifying comparator design by aiding in dynamic offset suppression. A $1{^{\text {st}}}$ -order NS-SAR ADC is implemented with the proposed DCMS scheme in a 0.18- $\mu $ m CMOS process. Measurement results indicate it can achieve a Signal-to-Noise-and-Distortion Ratio (SNDR) of 66.5 dB with a power consumption of $19.22~\mu $ W from a 1-V supply, at a sampling rate of 1 MS/s. This yields a Schreier Figure-of-Merit (FoMs) of 161.6 dB and a Walden Figure-of-Merit (FoMw) of 89.28 fJ/conversion-step.