Riadh Ayachi , Mouna Afif , Yahia Said , Abdessalem Ben Abdelali
{"title":"Lightweight path aggregation network for pedestrian detection on FPGA board","authors":"Riadh Ayachi , Mouna Afif , Yahia Said , Abdessalem Ben Abdelali","doi":"10.1016/j.jpdc.2025.105137","DOIUrl":null,"url":null,"abstract":"<div><div>In urban environments, pedestrian safety stands as a pivotal metric dictating the accuracy and efficacy of cutting-edge technologies like Advanced Driver Assistance Systems (ADAS) and autonomous vehicles. However, the deployment of such technologies introduces various constraints, notably including the computational resources of processing boards. Therefore, constructing a robust pedestrian detection system necessitates achieving a delicate balance between performance and computational complexity. In this study, we propose the development of a lightweight Convolutional Neural Network (CNN) model specifically tailored for pedestrian detection. The backbone architecture of the model was meticulously searched using a network search engine predicated on the Multi-Objective Genetic Algorithm (NSGA-II) with a customized strategy. Notably, we shifted the search space from central processing units to Multi-Processor System-on-Chip (MPSoC) devices, aligning with the practical considerations of real-world applications. Our proposed model capitalizes on the path aggregation architecture coupled with a lightweight backbone design. The core concept revolves around the efficient transfer of high semantic features from the network's bottom to its top via the shortest path, thereby enhancing detection rates without introducing undue computational complexity. To ensure compatibility with embedded devices with limited memory, the proposed model underwent compression via quantization and pruning techniques. For rigorous evaluation, we tested the pedestrian detection model on the Xilinx ZCU 102 board, utilizing the Karlsruhe Institute of Technology and Toyota Technological Institute (KITTI) dataset for training and evaluation purposes. The reported results substantiate the efficacy of our proposed model, boasting a mean average precision (mAP) of 93.6 % alongside a commendable processing speed of 13 frames per second (FPS). These outcomes underscore the suitability of the proposed model for real-life scenarios, wherein ensuring a high level of safety remains paramount.</div></div>","PeriodicalId":54775,"journal":{"name":"Journal of Parallel and Distributed Computing","volume":"204 ","pages":"Article 105137"},"PeriodicalIF":3.4000,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Parallel and Distributed Computing","FirstCategoryId":"94","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0743731525001042","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"COMPUTER SCIENCE, THEORY & METHODS","Score":null,"Total":0}
引用次数: 0
Abstract
In urban environments, pedestrian safety stands as a pivotal metric dictating the accuracy and efficacy of cutting-edge technologies like Advanced Driver Assistance Systems (ADAS) and autonomous vehicles. However, the deployment of such technologies introduces various constraints, notably including the computational resources of processing boards. Therefore, constructing a robust pedestrian detection system necessitates achieving a delicate balance between performance and computational complexity. In this study, we propose the development of a lightweight Convolutional Neural Network (CNN) model specifically tailored for pedestrian detection. The backbone architecture of the model was meticulously searched using a network search engine predicated on the Multi-Objective Genetic Algorithm (NSGA-II) with a customized strategy. Notably, we shifted the search space from central processing units to Multi-Processor System-on-Chip (MPSoC) devices, aligning with the practical considerations of real-world applications. Our proposed model capitalizes on the path aggregation architecture coupled with a lightweight backbone design. The core concept revolves around the efficient transfer of high semantic features from the network's bottom to its top via the shortest path, thereby enhancing detection rates without introducing undue computational complexity. To ensure compatibility with embedded devices with limited memory, the proposed model underwent compression via quantization and pruning techniques. For rigorous evaluation, we tested the pedestrian detection model on the Xilinx ZCU 102 board, utilizing the Karlsruhe Institute of Technology and Toyota Technological Institute (KITTI) dataset for training and evaluation purposes. The reported results substantiate the efficacy of our proposed model, boasting a mean average precision (mAP) of 93.6 % alongside a commendable processing speed of 13 frames per second (FPS). These outcomes underscore the suitability of the proposed model for real-life scenarios, wherein ensuring a high level of safety remains paramount.
期刊介绍:
This international journal is directed to researchers, engineers, educators, managers, programmers, and users of computers who have particular interests in parallel processing and/or distributed computing.
The Journal of Parallel and Distributed Computing publishes original research papers and timely review articles on the theory, design, evaluation, and use of parallel and/or distributed computing systems. The journal also features special issues on these topics; again covering the full range from the design to the use of our targeted systems.