Image encryption architecture exploiting finite-precision error for System-on-Chip and programmable logic devices

Abstract

Security in interconnected System-on-Chip (SoC) devices is increasingly critical as their adoption expands, driving demand for cryptographic solutions that are both robust and cost-effective. Hence, this work addresses the challenges of implementing chaos-based encryption schemes on digital hardware by introducing a novel image encryption approach based on the mathematical complexity of Chua’s circuit. It exploits finite-precision computational errors as a noise-like entropy source within the encryption process. Using High-Level Synthesis (HLS) with C/C$++$, we implement two parallelized Digital Chua’s Circuits (DCCs), each numerically resolved via the fourth-order Runge–Kutta method and using distinct natural interval extensions. The lower-bound error is then extracted from the chaotic circuits and used to generate the final keystream. Optimized for IEEE-754 floating-point arithmetic, our stream cipher enables efficient hardware synthesis and achieves high cryptographic performance, reaching the target error threshold within a few clock cycles. The proposed image encryption design passes the NIST SP 800-22 test suite and achieves strong NPCR and UACI scores (over 99.6 % and 33.4 %, respectively), demonstrating efficiency and robustness against common attacks. Moreover, implemented on a ZCU104 evaluation board, the architecture can process one pixel in just 70 clock cycles with a low energy cost of 0.42 $\mu J$ using only 48 DSPs (2.48 % of available resources). By bridging chaotic dynamics and practical SoC architectures, this work provides an encryption solution that balances hardware consumption and energy efficiency.