Method for Suppressing Gate Voltage Oscillations in Magnetically Coupled Gate Drives for Series-Connected Power Semiconductor Devices

IF 0.4 4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Electrical Engineering in Japan Pub Date : 2025-04-30 DOI:10.1002/eej.23511

Takahiro Urakabe, Taiki Kanda, Makoto Hagiwara, Yusuke Higaki, Yuki Itogawa

引用次数: 0

Abstract

This study examines the gate magnetic coupling technique, a gate drive technology for series-connected power semiconductor devices, and discusses the generation principle of gate voltage oscillation specific to the technique and its countermeasures. Additionally, this study proposes two gate-drive circuits designed to suppress gate voltage oscillation. The experimental results obtained using 3.3 kV/750 A SiC-MOSFET/SiC-SBD power modules demonstrate that the proposed methods can suppress gate voltage oscillation and reduce the voltage imbalance between the series-connected elements.

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抑制串联功率半导体器件磁耦合栅极驱动器中栅极电压振荡的方法

本文研究了一种用于串联功率半导体器件的栅极驱动技术——栅极磁耦合技术，并讨论了该技术特有的栅极电压振荡的产生原理及其应对措施。此外，本研究提出两种栅极驱动电路来抑制栅极电压振荡。在3.3 kV/750 A SiC-MOSFET/SiC-SBD功率模块上的实验结果表明，该方法可以抑制栅极电压振荡，降低串联元件之间的电压不平衡。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Electrical Engineering in Japan 工程技术-工程：电子与电气

CiteScore

0.80

自引率

0.00%

发文量

审稿时长

4-8 weeks

期刊介绍： Electrical Engineering in Japan (EEJ) is an official journal of the Institute of Electrical Engineers of Japan (IEEJ). This authoritative journal is a translation of the Transactions of the Institute of Electrical Engineers of Japan. It publishes 16 issues a year on original research findings in Electrical Engineering with special focus on the science, technology and applications of electric power, such as power generation, transmission and conversion, electric railways (including magnetic levitation devices), motors, switching, power economics.