{"title":"Z Packed U-Cell Modular Multilevel Converter for STATCOM Applications","authors":"Sandy Atanalian;Fadia Sebaaly;Rawad Zgheib;Kamal Al-Haddad","doi":"10.1109/ACCESS.2025.3566015","DOIUrl":null,"url":null,"abstract":"The Modular Multilevel Converter (MMC) is a promising topology for STATCOM applications due to its key features, such as modularity, scalability, and reduced harmonic content. Increasing the number of voltage levels in MMC reduces harmonics but simultaneously increases the number of submodules (SMs) per arm, leading to larger sizes and higher costs, which presents a challenge. To address this, this article introduces a novel 17-level MMC-STATCOM based on the Z Packed U-Cell (ZPUC) converter as its SM, which enables the generation of more voltage levels with fewer components and reduced harmonic content, offering significant advantages in terms of size and cost. Given the complex structure of the proposed converter and the associated challenges in building a physical prototype, real-time (RT) simulation using FPGA technology is employed for validation. The key contributions include integrating the ZPUC-SM into a three-phase STATCOM for the first time and adapting the converter model and its control system to RT tools, including RT-LAB with an electric hardware solver for FPGA execution. In addition, capacitor voltage balancing and energy sorting algorithms are integrated within Phase-Shift Pulse Width Modulation, eliminating the need for an additional controller while maintaining the floating capacitors of ZPUC-SMs balanced and regulated. The specifications of the proposed converter are defined, the mathematical model and control system are derived, and a real-time implementation based on CPU and FPGA execution is built to verify the scheme. The obtained RT simulation results provide practical evidence confirming the effective operation of the proposed scheme in VAR compensation mode.","PeriodicalId":13079,"journal":{"name":"IEEE Access","volume":"13 ","pages":"78795-78807"},"PeriodicalIF":3.4000,"publicationDate":"2025-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10981426","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Access","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10981426/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, INFORMATION SYSTEMS","Score":null,"Total":0}
引用次数: 0
Abstract
The Modular Multilevel Converter (MMC) is a promising topology for STATCOM applications due to its key features, such as modularity, scalability, and reduced harmonic content. Increasing the number of voltage levels in MMC reduces harmonics but simultaneously increases the number of submodules (SMs) per arm, leading to larger sizes and higher costs, which presents a challenge. To address this, this article introduces a novel 17-level MMC-STATCOM based on the Z Packed U-Cell (ZPUC) converter as its SM, which enables the generation of more voltage levels with fewer components and reduced harmonic content, offering significant advantages in terms of size and cost. Given the complex structure of the proposed converter and the associated challenges in building a physical prototype, real-time (RT) simulation using FPGA technology is employed for validation. The key contributions include integrating the ZPUC-SM into a three-phase STATCOM for the first time and adapting the converter model and its control system to RT tools, including RT-LAB with an electric hardware solver for FPGA execution. In addition, capacitor voltage balancing and energy sorting algorithms are integrated within Phase-Shift Pulse Width Modulation, eliminating the need for an additional controller while maintaining the floating capacitors of ZPUC-SMs balanced and regulated. The specifications of the proposed converter are defined, the mathematical model and control system are derived, and a real-time implementation based on CPU and FPGA execution is built to verify the scheme. The obtained RT simulation results provide practical evidence confirming the effective operation of the proposed scheme in VAR compensation mode.
IEEE AccessCOMPUTER SCIENCE, INFORMATION SYSTEMSENGIN-ENGINEERING, ELECTRICAL & ELECTRONIC
CiteScore
9.80
自引率
7.70%
发文量
6673
审稿时长
6 weeks
期刊介绍:
IEEE Access® is a multidisciplinary, open access (OA), applications-oriented, all-electronic archival journal that continuously presents the results of original research or development across all of IEEE''s fields of interest.
IEEE Access will publish articles that are of high interest to readers, original, technically correct, and clearly presented. Supported by author publication charges (APC), its hallmarks are a rapid peer review and publication process with open access to all readers. Unlike IEEE''s traditional Transactions or Journals, reviews are "binary", in that reviewers will either Accept or Reject an article in the form it is submitted in order to achieve rapid turnaround. Especially encouraged are submissions on:
Multidisciplinary topics, or applications-oriented articles and negative results that do not fit within the scope of IEEE''s traditional journals.
Practical articles discussing new experiments or measurement techniques, interesting solutions to engineering.
Development of new or improved fabrication or manufacturing techniques.
Reviews or survey articles of new or evolving fields oriented to assist others in understanding the new area.