CVEC: A customized VIS-based equivalence checker for verifying commercial field-programmable gate array synthesis software in small modular reactors

Abstract

Field-programmable gate array (FPGA) is a hardware-based platform widely used in safety-related systems. FPGA development involves synthesis, placement and routing, with designs ultimately downloaded onto the device. Commercial FPGA synthesis software converts register-transfer level (RTL) designs into gate-level representations. Standards such as NUREG/CR-6421, IEEE Std 7-4.3.2, EPRI NP-5652, and EPRI TR-106439 require verification of these tools, while IEC 62566 mandates static analysis, including equivalence checking, for nuclear power plant applications. This paper introduces CVEC, a customized VIS-based equivalence checker that verifies the correctness of FPGA synthesis software. It performs equivalence checking between RTL designs and gate-level designs synthesized using Synopsys Synplify Pro within the Libero IDE. When verification is successful, it ensures that these softwares operate correctly at the synthesis level. Two case studies demonstrate the effectiveness of CVEC in verifying the functional correctness of commercial FPGA synthesis softwares.