Memory-efficient programmable packet parsing for multi-tenant terabit networks

Abstract

Programmable data plane architectures such as RMT and dRMT obtain great attention due to their flexibility in processing packets on demand without modifying the switch chip design. Unfortunately, the packet parser, as a crucial component, suffers from low processing performance and large logic usage. Existing programmable packet parser design utilizes a Finite State Machine (FSM) to parse the packet header vector (PHV) in a loop manner, or enumerates all possible protocol paths to extract the packet header vector in parallel, which leads to low throughput or significant consumption of T-CAM resources.

This paper proposes the partition parser (PParser), a novel programmable parser design, working in multi-tenant networks, that makes the best trade-offs between the parsing performance and the resource usage as far as we are concerned. To maximize the performance, PParser initiates the protocol path analysis in compile-time and parses packets in parallel using T-CAM. To avoid the path explosion without reducing performance, PParser efficiently partitions the parsing graph into sub-graphs and leverages a multi-stage T-CAM for cascade parsing. The performance, flexibility, and resource usage of PParser are excessively evaluated using real-world protocols on the FPGA prototype. The result shows that PParser achieves 3.98$\times$ throughput compared with the FSM-based parser and 87% compression rate and a similar throughput compared with HyperParser.