Exploring low overhead fingerprint biometric watermark for loop pipelined hardware IPs during behavioral synthesis

Abstract

Loop based applications form an integral component in several consumer electronics systems as hardware intellectual property (IP) cores. Some powerful examples include finite impulse response filter cores, convolution filters etc. For enhanced performance and increased security of hardware IPs, handling loops efficiently while embedding low-cost security information (watermark) as digital evidence is the key. Robust security watermark embedded as digital evidence in the IP cores of CE systems, ensures sturdy detective countermeasure against piracy and counterfeiting, assuring the safety of end consumer. This paper presents a novel behavioral synthesis/high-level synthesis (HLS) based low-cost fingerprint biometric-watermark embedded security methodology for loop pipelined hardware IPs of CE systems. More explicitly, the paper presents the following novel contributions: a) exploration of low overhead fingerprint biometric-watermark embedded security watermark during HLS; b) embedding low-cost fingerprint based security constraints in loop pipelined IP designs used in CE systems; c) enhanced security against IP piracy (pirated designs) from an SoC integrator's and CE systems designers' perspective in terms of digital evidence (resulting into greater tamper tolerance ability, probability of coincidence and entropy) than prior similar approaches, at nominal design overhead.