{"title":"On-chip kernel-based spatial filter for CMOS image sensor","authors":"Bárbaro Maykel López-Portilla Vigil , Wladimir Valenzuela , Payman Zarkesh-Ha , Miguel Figueroa","doi":"10.1016/j.compeleceng.2025.110218","DOIUrl":null,"url":null,"abstract":"<div><div>The Internet of Things is transforming our interactions with the world. CMOS Image Sensors are crucial components in multimedia applications for the Internet of Things. They allow IoT devices to perceive, interpret, and respond to the physical world, improving efficiency, safety, and convenience across various industries. The images captured by these sensors are sent to an external digital device for processing. This data flow can result in high power consumption, limit the frame rate, and restrict the parallelization of algorithm data. This paper introduces a new CMOS Smart Imaging Sensor architecture that performs kernel-based spatial filtering at the pixel level, overcoming the drawbacks above. The design proposal enables spatial filtering using a single kernel, two different kernels on the same image, or two cascaded kernels. The circuit calculates the absolute value of the single convolution in parallel at each pixel using simple arithmetic operations within a neighborhood during photocurrent integration. This process is repeated when the filter requires more than one kernel. We designed a 128 × 128-pixel imager in a <span><math><mrow><mn>0</mn><mo>.</mo><mn>35</mn><mspace></mspace><mi>μ</mi><mi>m</mi></mrow></math></span> CMOS process and validated it through post-layout simulations. According to these simulations, the kernel-based spatial filter circuit is integrated into the imager, which processes images at frame rates ranging from 746 to 752 fps. Our CMOS implementation outperforms state-of-the-art circuits in denoising, with the best result: a Mean Squared Error of 0.90, Peak Signal Noise Ratio of 48.55 dB, and Structural Similarity Index Metric of 0.99 configured as the mean filter. Additionally, it demonstrates comparable performance in edge detection to state-of-the-art circuits. The best results were achieved with a Mean Squared Error of 4.68, a Peak Signal to Noise Ratio of 41.42 dB, and a Structural Similarity Index Metric of 0.97, using the y-direction Robert filter. Our proposed circuit demonstrated good edge-location accuracy, with a value of 0.99 for the Sobel filter, which is one of the best results according to the Pratt Figure of Merit.</div></div>","PeriodicalId":50630,"journal":{"name":"Computers & Electrical Engineering","volume":"123 ","pages":"Article 110218"},"PeriodicalIF":4.0000,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Computers & Electrical Engineering","FirstCategoryId":"94","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0045790625001612","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
The Internet of Things is transforming our interactions with the world. CMOS Image Sensors are crucial components in multimedia applications for the Internet of Things. They allow IoT devices to perceive, interpret, and respond to the physical world, improving efficiency, safety, and convenience across various industries. The images captured by these sensors are sent to an external digital device for processing. This data flow can result in high power consumption, limit the frame rate, and restrict the parallelization of algorithm data. This paper introduces a new CMOS Smart Imaging Sensor architecture that performs kernel-based spatial filtering at the pixel level, overcoming the drawbacks above. The design proposal enables spatial filtering using a single kernel, two different kernels on the same image, or two cascaded kernels. The circuit calculates the absolute value of the single convolution in parallel at each pixel using simple arithmetic operations within a neighborhood during photocurrent integration. This process is repeated when the filter requires more than one kernel. We designed a 128 × 128-pixel imager in a CMOS process and validated it through post-layout simulations. According to these simulations, the kernel-based spatial filter circuit is integrated into the imager, which processes images at frame rates ranging from 746 to 752 fps. Our CMOS implementation outperforms state-of-the-art circuits in denoising, with the best result: a Mean Squared Error of 0.90, Peak Signal Noise Ratio of 48.55 dB, and Structural Similarity Index Metric of 0.99 configured as the mean filter. Additionally, it demonstrates comparable performance in edge detection to state-of-the-art circuits. The best results were achieved with a Mean Squared Error of 4.68, a Peak Signal to Noise Ratio of 41.42 dB, and a Structural Similarity Index Metric of 0.97, using the y-direction Robert filter. Our proposed circuit demonstrated good edge-location accuracy, with a value of 0.99 for the Sobel filter, which is one of the best results according to the Pratt Figure of Merit.
期刊介绍:
The impact of computers has nowhere been more revolutionary than in electrical engineering. The design, analysis, and operation of electrical and electronic systems are now dominated by computers, a transformation that has been motivated by the natural ease of interface between computers and electrical systems, and the promise of spectacular improvements in speed and efficiency.
Published since 1973, Computers & Electrical Engineering provides rapid publication of topical research into the integration of computer technology and computational techniques with electrical and electronic systems. The journal publishes papers featuring novel implementations of computers and computational techniques in areas like signal and image processing, high-performance computing, parallel processing, and communications. Special attention will be paid to papers describing innovative architectures, algorithms, and software tools.