Design and implementation of dummy fill for chemical-mechanical polishing in superconducting single flux quantum circuit fabrication process

Abstract

We present the development of a planarized fabrication process for large-scale Single Flux Quantum (RSFQ) circuits, termed “SIMIT Nb03b.” This process utilizes chemical-mechanical polishing (CMP) to planarize the SiO₂ interlayer dielectric, enabling reduced feature sizes and improved scalability. Dummy fill has proven to be an effective technique for reducing process variation and to improve planarization for chemical mechanical polishing, however, few studies have been reported on how to determine the appropriate fill pattern for superconducting integrated process. In this work, dummy fill structures were strategically placed outside the circuit region to minimize their impact on the circuit's logical functionality. Then we determine the pattern density of dummy fill based on the standard cell library of the process and a fill pattern density of 45 %, length of 7 μm, and spacing of 3.5 μm between each other is chosen. Experimental results show that, at this dummy fill setup, the non-uniformity of the SiO₂ film thickness after CMP is <5 %. We also developed an indirect method for assessing the residual SiO₂ thickness in circuit regions after CMP, which overcomes the limitations of direct measurement on small, narrow circuit patterns. This method enhanced the accuracy of measuring the residual SiO₂ film thickness in circuit regions by over 50 % compared to direct measurement techniques. The SIMIT Nb03b process has achieved a critical current of 6 kA/cm² and supported junction sizes down to 0.4 μm, small-scale superconducting integrated circuits fabricated by this process demonstrated a sufficiently wide operating margin, validating the efficacy of the developed fabrication technology.