A Novel Approach to Test-Induced Defect Detection in Semiconductor Wafers, Using Graph-Based Semi-Supervised Learning (GSSL)

Abstract

The semiconductor industry plays a vital role in modern technology, with semiconductor devices embedded in almost all electronic products. As these devices become increasingly complex, ensuring quality and reliability poses significant challenges. Electrical testing on semiconductor wafers for defects is crucial, but paradoxically, the testing process itself can introduce defects. These test-induced defects could remain undetected on the wafer, proceed through assembly, and may only be discovered later by customers, leading to returns and significant yield loss. This study proposes a novel graph-based semi-supervised learning (GSSL) algorithm to identify these test-induced hidden defects on the semiconductor wafer that escape conventional methods. The algorithm, which incorporates domain knowledge in creating a graph representation of wafer, and utilizing a weighted edge label propagation model, has demonstrated its effectiveness by achieving a 68% accuracy on a real-world dataset, offering a promising approach to enhance quality control in semiconductor manufacturing.