Deep learning driven silicon wafer defect segmentation and classification

Abstract

Integrated Circuits are made of various transistors that are embedded on a silicon wafer, these wafers are difficult to process and hence are prone to defects. Defecting these defects manually is a time consuming and labour-intensive task and hence automation is necessary. Deep Learning approach is better suited in this case as it is able to generalize defects if trained properly and can be a solution to segmentation and classification of defects automatically. The segmentation model mentioned in this study achieved a Mean Absolute Error (MAE) of 0.0036, a Root Mean Squared Error (RMSE) of 0.0576, a Dice Index (DSC) of 0.7731, and an Intersection over Union (IoU) of 0.6590. The classification model achieved 0.9705 Accuracy, 0.9678 Precision, 0.9705 Recall, and 0.9676 F1 Score. In order to make this process a more interactive, an LLM with Q&A capabilities was integrated to solve any doubts and answer any questions regarding defects in wafers.

This approach helps automate the detection process thus improving quality of end product.

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  Successful and precise defect segmentation and classification using Deep Learning was achieved.
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  High-intensity regions after post-processing.
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  An LLM offering defect analysis and guidance was streamlined.