Scalable Matrix Decomposition-Based Less-Complex HEVC Transform Architecture

Abstract

High Efficiency Video Coding (HEVC) is widely used in ultra-high definition (UHD) video applications for its high compression ability, and Discrete Cosine Transform (DCT) is an indispensable module in it. With increasing video resolution, DCT sizes and hardware complexity increase continuously, which poses challenges to the system designers, especially when real-time operations are required. Therefore, the low-complexity approximation of the DCT is paramount in applications demanding real-time computation. To meet this requirement, this article proposes a new DCT architecture for HEVC based on the matrix decomposition method. Each coefficient of the resultant matrices is approximated in such a way that all the multiplications can be realized by shift and add operations. The method reduces the data path width and number of cascaded adders as the matrices use small coefficients compared to the integer DCT of HEVC. The proposed approach designs all transform sizes and maintains the scalability features of DCT used in HEVC. At the cost of a minor drop in PSNR, the proposed method requires 74% less area-delay product in comparison to the HEVC reference algorithm. It is capable of processing at least 30 frames/s of UHD video when implemented on the FPGA of a 28 nm technology node.