Triple and quadruple metal gate work function engineering to improve the performance of junctionless double surrounding gate In0.53Ga0.47As nanotube MOSFET for the upcoming Sub 3 nm technology node

Abstract

In line with Moore's Law and the International Roadmap for Devices and Systems (IDRS), shrinking MOSFET dimensions to the 3 nm technology node requires the introduction and thorough investigation of new device structures and advanced materials. The current study focuses on the implementation of Triple Metal (TM) and Quadruple Metal (QM) gate work function engineering techniques on both junctionless (JL) and inversion mode (IM) Double surrounding Gate (DSG) In_0.53Ga_0.47As nanotube (NT) MOSFET. The objective is to analyze the drain current (I_D) characteristics for a gate length of 3 nm using Silvaco ATLAS 3D TCAD. In order to make a fair comparison between JL and IM In_0.53Ga_0.47As NT, the doping concentration of TM and QM JL In_0.53Ga_0.47As NT is tuned to achieve two specific objectives. Firstly, the goal is to produce the same I_ON as IM In_0.53Ga_0.47As NT. Secondly, the aim is to achieve the same threshold voltage (V_TH) as IM In_0.53Ga_0.47As NT. It was discovered that the I_OFF for JL devices is approximately 2.93 times smaller compared to IM devices in the TM situation, while considering matching I_ON and V_TH. The JL devices have an I_OFF that is 12.9 times smaller and an I_OFF that is 10² times smaller compared to the IM device for the QM situation. This is achieved by matching the I_ON and V_TH values. It achieves a lesser drain-induced barrier lowering (DIBL) of approximately 28.10 mV/V, a virtually perfect subthreshold slope (SS) of roughly 60mV/dec, and a larger current ratio of I_ON/I_OFF, which is approximately 1.42 × 10⁷.