TrieKV: A High-Performance Key-Value Store Design With Memory as Its First-Class Citizen

IF 5.6 2区 计算机科学 Q1 COMPUTER SCIENCE, THEORY & METHODS
Hui Sun;Deyan Kong;Song Jiang;Yinliang Yue;Xiao Qin
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引用次数: 0

Abstract

Key-value (KV) stores based on log-structured merge tree (LSM-tree) have been extensively studied and deployed in major information technology infrastructures. Because this type of systems is catered for KV store accessing disks, a limited disk bandwidth increases the difficulty of serving online data requests. One solution involves using a large DRAM such that frequent KV pairs are buffered and accessed from the main memory – and this solution exposes a major design drawback of the KV store: its lack of support for integrated data management in memory and on disks. For example, data in the most popular LSM-tree implementation – RocksDB – may reside in a small write buffer (MemTable) that organizes KV pairs for disk writes, a buffer cache for disk blocks, a write-ahead log on the disk for data persistence, and in various LSM levels on the disk. Without the integrated management of indexes, data, and their persistence in a hierarchical memory/disk architecture, memory is under-utilized along with missed performance optimization opportunities. We propose a KV store, TrieKV, which holistically incorporates DRAM, persistent memory (PMem), and disk with certain desired features: (1) fast in-memory access, (2) accurate identification of hot/cold data at an adaptable granularity, (3) customized memory space allocation for minimized fragmentation, (4) hotness-aware data placement across the storage hierarchy, (5) in-place data persistence in the PMem, and (6) hotness-aware LSM-tree compaction. TrieKV employs a single, integrated trie-structured index for all KV pairs in memory, where access hotness can be consistently discovered. Accordingly, the KV placement is dynamically determined according to the hotness and persistence needs of the storage hierarchy spanning the DRAM, PMem, and solid-state drive. In the experiment, we demonstrate that the 99th latency of RocksDB and NoveLSM is 38x and 6x higher than that of TrieKV, respectively. In addition, TrieKV outperforms RocksDB and NoveLSM by a factor of 5.6 and 1.7in terms of throughput, respectively.
TrieKV:以内存为头等公民的高性能键值存储设计
基于日志结构合并树(LSM-tree)的键值(KV)存储已被广泛研究并部署在主要的信息技术基础设施中。由于这类系统是针对访问磁盘的 KV 存储,有限的磁盘带宽增加了服务在线数据请求的难度。一种解决方案是使用大型 DRAM,对频繁出现的 KV 对进行缓冲,然后从主存储器进行访问--这种解决方案暴露了 KV 存储的一个主要设计缺陷:不支持存储器和磁盘上的集成数据管理。例如,在最流行的 LSM 树实现(RocksDB)中,数据可能存在于一个小的写缓冲区(MemTable)中,该缓冲区用于组织磁盘写入的 KV 对、磁盘块的缓冲缓存、磁盘上用于数据持久化的先写日志以及磁盘上的各种 LSM 层中。如果不对分层内存/磁盘架构中的索引、数据及其持久性进行集成管理,内存就会利用率低下,并错失性能优化机会。我们提出了一种 KV 存储,即 TrieKV,它全面整合了 DRAM、持久内存(PMem)和磁盘,并具有某些所需的功能:(1) 快速内存访问,(2) 以适应性粒度准确识别热/冷数据,(3) 自定义内存空间分配以最小化碎片,(4) 在整个存储层次结构中进行热感知数据放置,(5) 在 PMem 中进行就地数据持久化,(6) 热感知 LSM 树压缩。TrieKV 对内存中的所有 KV 对采用单一的集成三元结构索引,可以持续发现访问热度。因此,KV 位置是根据跨越 DRAM、PMem 和固态硬盘的存储层次的热度和持久性需求动态决定的。实验证明,RocksDB 和 NoveLSM 的第 99 次延迟分别是 TrieKV 的 38 倍和 6 倍。此外,就吞吐量而言,TrieKV分别比RocksDB和NoveLSM高出5.6倍和1.7倍。
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来源期刊
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems 工程技术-工程:电子与电气
CiteScore
11.00
自引率
9.40%
发文量
281
审稿时长
5.6 months
期刊介绍: IEEE Transactions on Parallel and Distributed Systems (TPDS) is published monthly. It publishes a range of papers, comments on previously published papers, and survey articles that deal with the parallel and distributed systems research areas of current importance to our readers. Particular areas of interest include, but are not limited to: a) Parallel and distributed algorithms, focusing on topics such as: models of computation; numerical, combinatorial, and data-intensive parallel algorithms, scalability of algorithms and data structures for parallel and distributed systems, communication and synchronization protocols, network algorithms, scheduling, and load balancing. b) Applications of parallel and distributed computing, including computational and data-enabled science and engineering, big data applications, parallel crowd sourcing, large-scale social network analysis, management of big data, cloud and grid computing, scientific and biomedical applications, mobile computing, and cyber-physical systems. c) Parallel and distributed architectures, including architectures for instruction-level and thread-level parallelism; design, analysis, implementation, fault resilience and performance measurements of multiple-processor systems; multicore processors, heterogeneous many-core systems; petascale and exascale systems designs; novel big data architectures; special purpose architectures, including graphics processors, signal processors, network processors, media accelerators, and other special purpose processors and accelerators; impact of technology on architecture; network and interconnect architectures; parallel I/O and storage systems; architecture of the memory hierarchy; power-efficient and green computing architectures; dependable architectures; and performance modeling and evaluation. d) Parallel and distributed software, including parallel and multicore programming languages and compilers, runtime systems, operating systems, Internet computing and web services, resource management including green computing, middleware for grids, clouds, and data centers, libraries, performance modeling and evaluation, parallel programming paradigms, and programming environments and tools.
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