State-Space Modeling and Validation of Circuit Parasitics' Effect on the Performance of a High-Gain Nonisolated Switched Inductor Topology

Abstract

High-gain dc-dc converters are becoming popular in various applications such as uninterruptible power supplies, grid integration, electric vehicles, etc. Analysis of the voltage gain, stability, and sensitivity factors of the high-gain dc-dc converters is essential in comparison with conventional dc-dc converters, primarily due to the increased number of passive components. In order to analyze these factors, different small-signal models are well-established for conventional dc-dc converters. However, these models do not consider all the effects of circuit parasitics. This article presents a detailed small-signal modeling of high-gain nonisolated switched inductor (NISI) and conventional boost converter topologies, taking into account all the effects of circuit parasitics. Further, the effect of circuit parasitics on the small-signal control-to-output transfer function and voltage gain of the high-gain NISI topology is highlighted. Later, simulation studies are carried-out on the high-gain NISI and conventional boost dc-dc converters, and the results are presented. Finally, the prototypes of the converters are fabricated, and experimental studies are carried-out to ascertain the results obtained from simulations. The measured maximum efficiency of the high-gain NISI converter is 95% at a power rating of 600 W.