Enhancing interconnection network topology for chiplet-based systems: An automated design framework

IF 6.2 2区 计算机科学 Q1 COMPUTER SCIENCE, THEORY & METHODS
Zhipeng Cao , Qinrang Liu , Zhiquan Wan , Wenbo Zhang , Ke Song , Wenbin Liu
{"title":"Enhancing interconnection network topology for chiplet-based systems: An automated design framework","authors":"Zhipeng Cao ,&nbsp;Qinrang Liu ,&nbsp;Zhiquan Wan ,&nbsp;Wenbo Zhang ,&nbsp;Ke Song ,&nbsp;Wenbin Liu","doi":"10.1016/j.future.2024.107547","DOIUrl":null,"url":null,"abstract":"<div><div>Chiplet-based systems integrate discrete chips on an interposer and use the interconnection network to enable communication between different components. The topology of the interconnection network poses a significant challenge to overall performance, as it can greatly affect both latency and throughput. However, the design of the interconnection network topology is not currently automated. They rely heavily on expert knowledge and fail to deliver optimal performance. To this end, we propose an automated design framework for chiplet interconnection network topology, called CINT-AD. To implement CINT-AD, we first investigate topology-related properties from the perspective of design constraints and structural symmetry. Then, using these properties, we develop an automated framework to generate the topology for interposer interconnections between different chiplets. A deadlock-free routing scheme is proposed for the topologies generated by CINT-AD to fully utilize the resources of the interconnection network. Experimental results show that CINT-AD achieves lower average latency and higher throughput compared to existing state-of-the-art topologies. Furthermore, power and area analysis show that the overhead of CINT-AD is negligible.</div></div>","PeriodicalId":55132,"journal":{"name":"Future Generation Computer Systems-The International Journal of Escience","volume":"163 ","pages":"Article 107547"},"PeriodicalIF":6.2000,"publicationDate":"2024-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Future Generation Computer Systems-The International Journal of Escience","FirstCategoryId":"94","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167739X24005119","RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"COMPUTER SCIENCE, THEORY & METHODS","Score":null,"Total":0}
引用次数: 0

Abstract

Chiplet-based systems integrate discrete chips on an interposer and use the interconnection network to enable communication between different components. The topology of the interconnection network poses a significant challenge to overall performance, as it can greatly affect both latency and throughput. However, the design of the interconnection network topology is not currently automated. They rely heavily on expert knowledge and fail to deliver optimal performance. To this end, we propose an automated design framework for chiplet interconnection network topology, called CINT-AD. To implement CINT-AD, we first investigate topology-related properties from the perspective of design constraints and structural symmetry. Then, using these properties, we develop an automated framework to generate the topology for interposer interconnections between different chiplets. A deadlock-free routing scheme is proposed for the topologies generated by CINT-AD to fully utilize the resources of the interconnection network. Experimental results show that CINT-AD achieves lower average latency and higher throughput compared to existing state-of-the-art topologies. Furthermore, power and area analysis show that the overhead of CINT-AD is negligible.
增强基于芯片组系统的互连网络拓扑结构:自动设计框架
基于 Chiplet 的系统将分立芯片集成在中间件上,并利用互连网络实现不同组件之间的通信。互连网络的拓扑结构会极大地影响延迟和吞吐量,因此对整体性能构成重大挑战。然而,互连网络拓扑结构的设计目前尚未实现自动化。它们严重依赖专家知识,无法提供最佳性能。为此,我们提出了一种芯片组互连网络拓扑自动设计框架,称为 CINT-AD。为了实现 CINT-AD,我们首先从设计约束和结构对称的角度研究了拓扑相关特性。然后,利用这些特性,我们开发了一个自动框架,用于生成不同芯片间的互联拓扑。针对 CINT-AD 生成的拓扑结构,我们提出了一种无死锁路由方案,以充分利用互连网络的资源。实验结果表明,与现有的最先进拓扑相比,CINT-AD 实现了更低的平均延迟和更高的吞吐量。此外,功率和面积分析表明,CINT-AD 的开销可以忽略不计。
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来源期刊
CiteScore
19.90
自引率
2.70%
发文量
376
审稿时长
10.6 months
期刊介绍: Computing infrastructures and systems are constantly evolving, resulting in increasingly complex and collaborative scientific applications. To cope with these advancements, there is a growing need for collaborative tools that can effectively map, control, and execute these applications. Furthermore, with the explosion of Big Data, there is a requirement for innovative methods and infrastructures to collect, analyze, and derive meaningful insights from the vast amount of data generated. This necessitates the integration of computational and storage capabilities, databases, sensors, and human collaboration. Future Generation Computer Systems aims to pioneer advancements in distributed systems, collaborative environments, high-performance computing, and Big Data analytics. It strives to stay at the forefront of developments in grids, clouds, and the Internet of Things (IoT) to effectively address the challenges posed by these wide-area, fully distributed sensing and computing systems.
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