Scheduling of memory chips for final testing on parallel machines considering power constraints and deteriorating effects

IF 9.8 1区 工程技术 Q1 ENGINEERING, INDUSTRIAL
Shaojun Lu , Chiwei Hu , Min Kong , Amir M. Fathollahi-Fard , Maxim A. Dulebenets
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引用次数: 0

Abstract

This paper delves into the intricate scheduling strategies crucial for the final testing phase of memory chip manufacturing within the semiconductor industry and other related sectors. It specifically addresses the complex serial-batching scheduling problem, where memory chips are tested on parallel machines under power constraints and chip deterioration effects. The processing time for each chip is significantly influenced by both the cumulative processing time of preceding chips and the power requirements for testing. We formulate this real-world optimization problem using a mixed integer nonlinear programming model. Exact solutions for small instances are obtained using a commercial solver. However, due to the model's complexity, we also develop heuristic solutions to efficiently handle larger instances. Based on the derivation of structural properties, we develop two tailored heuristic algorithms to determine the schedule for the final testing of memory chips. Additionally, we propose a refined Variable Neighborhood Search algorithm (VNS-H) that seamlessly integrates five local search strategies with two supplementary heuristic algorithms, dynamically alternating between them to ensure a balance between computational efficiency and the quality of the solutions obtained. Additionally, we establish a lower bound to validate the effectiveness of these solutions, particularly for large-scale instances. To validate the efficacy and robustness of our proposed metaheuristic algorithm, we conduct a rigorous comparison of the VNS-H algorithm with five other metaheuristic algorithms that have promising performance in various optimization problems. The results highlight the superior performance of the VNS-H algorithm. In small-scale instances, our VNS-H algorithm achieves an average makespan that is 5.52% lower compared to the original VNS. For large-scale instances, the VNS-H algorithm reduces the average makespan by 13.46% compared to VNS. Finally, we discuss the managerial implications of our findings, providing insights specifically tailored to semiconductor manufacturing enterprises based on the outcomes of this study.
考虑到功率限制和劣化效应,在并行机器上为最终测试调度内存芯片
本文深入探讨了对半导体行业和其他相关行业内存芯片制造的最终测试阶段至关重要的复杂调度策略。本文特别讨论了复杂的串行批处理调度问题,即在功率限制和芯片劣化效应的情况下,在并行机器上对内存芯片进行测试。每个芯片的处理时间受前面芯片的累积处理时间和测试所需功率的显著影响。我们采用混合整数非线性编程模型来解决这个现实世界中的优化问题。使用商业求解器可以获得小实例的精确解。然而,由于模型的复杂性,我们还开发了启发式解决方案,以有效处理较大的实例。基于结构特性的推导,我们开发了两种量身定制的启发式算法,用于确定内存芯片最终测试的时间表。此外,我们还提出了一种改进的可变邻域搜索算法(VNS-H),该算法将五种局部搜索策略与两种辅助启发式算法无缝集成,动态交替使用,以确保计算效率与所获解决方案质量之间的平衡。此外,我们还建立了一个下限,以验证这些解决方案的有效性,尤其是对大规模实例的有效性。为了验证我们提出的元启发式算法的有效性和鲁棒性,我们将 VNS-H 算法与其他五种元启发式算法进行了严格的比较,这五种算法在各种优化问题中都有不俗的表现。结果凸显了 VNS-H 算法的优越性能。在小规模实例中,我们的 VNS-H 算法实现的平均时间跨度比原始 VNS 算法低 5.52%。在大规模实例中,VNS-H 算法比 VNS 算法平均缩短了 13.46%。最后,我们讨论了我们的研究结果对管理的影响,并根据本研究的结果提出了专门针对半导体制造企业的见解。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
International Journal of Production Economics
International Journal of Production Economics 管理科学-工程:工业
CiteScore
21.40
自引率
7.50%
发文量
266
审稿时长
52 days
期刊介绍: The International Journal of Production Economics focuses on the interface between engineering and management. It covers all aspects of manufacturing and process industries, as well as production in general. The journal is interdisciplinary, considering activities throughout the product life cycle and material flow cycle. It aims to disseminate knowledge for improving industrial practice and strengthening the theoretical base for decision making. The journal serves as a forum for exchanging ideas and presenting new developments in theory and application, combining academic standards with practical value for industrial applications.
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