A Fast and Efficient 191-bit Elliptic Curve Cryptographic Processor Using a Hybrid Karatsuba Multiplier for IoT Applications

IF 3.4 3区计算机科学 Q2 COMPUTER SCIENCE, INFORMATION SYSTEMS

IEEE Access Pub Date : 2024-10-03 DOI:10.1109/ACCESS.2024.3472650

Sumit Singh Dhanda;Brahmjit Singh;Chia-Chen Lin;Poonam Jindal;Deepak Panwar;Tarun Kumar Sharma;Saurabh Agarwal;Wooguil Pak

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引用次数: 0

Abstract

The most widely used asymmetric cipher is ECC. It can be applied to IoT applications to offer various security services. However, a wide range of sectors have been investigated for applying ECC. The field of elliptic curve cryptographic processors for GF (2191) has received less attention. This study presents a low-resource, high-efficiency architecture for a 191-bit ECC processor. This design uses a novel hybrid Karatsuba multiplier for the multiplication of finite fields. For GF (2191), the Quad-Itoh-Tsuji algorithm has been altered to provide a small-size inversion unit. PlanAhead software synthesizes the CPU, which is then implemented on several Xilinx FPGAs. With savings in slice consumption ranging from 16 to 43 percent, the implemented design is the most restricted compared to the current designs. Compared to previously published designs, it is 3.8–1000 times faster. The elliptic curve scalar multiplication on the Virtex-7 FPGA is computed in

$7.24~\mu $

s. Additionally, the proposed design achieves savings in area-time products of 77 to 90 percent. It may be beneficial for IoT edge devices. It utilizes 3120 mW of power for the operation. A state-of-the-art comparison based on the figure of merit (FoM) reveals that the proposed design outclasses the newest designs by a large margin. It also exhibits a throughput of 138.121 Kbps.

查看原文本刊更多论文

使用混合卡拉祖巴乘法器的快速高效 191 位椭圆曲线加密处理器，适用于物联网应用

使用最广泛的非对称密码是 ECC。它可应用于物联网应用，提供各种安全服务。然而，应用 ECC 的领域非常广泛。针对 GF (2191) 的椭圆曲线加密处理器领域受到的关注较少。本研究提出了一种低资源、高效率的 191 位 ECC 处理器架构。该设计使用新型混合卡拉祖巴乘法器进行有限域乘法运算。对于 GF (2191)，改变了 Quad-Itoh-Tsuji 算法，以提供一个小尺寸的反转单元。PlanAhead 软件对 CPU 进行综合，然后在多个 Xilinx FPGA 上实现。与现有设计相比，该设计节省了 16% 至 43% 的片耗，是限制最多的设计。与之前发布的设计相比，它的速度提高了 3.8-1000 倍。在 Virtex-7 FPGA 上计算椭圆曲线标量乘法只需 7.24~\mu $ s。它可用于物联网边缘设备。它的运行功耗为 3120 mW。基于优越性系数（FoM）的最新设计比较显示，所提出的设计大大超越了最新设计。它还显示出 138.121 Kbps 的吞吐量。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Access COMPUTER SCIENCE, INFORMATION SYSTEMSENGIN-ENGINEERING, ELECTRICAL & ELECTRONIC

CiteScore

9.80

自引率

7.70%

发文量

6673

审稿时长

6 weeks

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