Comparative analysis of Vedic multiplier using Vedic sutras with existing multipliers in biomedical application

Abstract

In today's computer world, a lot of real-time applications require rapid processing units. Arithmetic Logic Units (ALU) and Multiply-Accumulate (MAC) are the fundamental parts of these circuits and are necessary for their effective and rapid operation. The most significant prevalent part of digital signal processing devices is multipliers. The multiplier, adder, and registers need to be changed in order to maintain accuracy and increase execution speed, which will improve the performance of the ALU and MAC. The development of greater multipliers is being given priority for application in processors because of the increasing constraints on latency. To accelerate multiplication, it is essential to develop quicker multipliers. Vedic multipliers are preferred over different current expansions due to their low power consumption, fast operation, and efficient use of space. Vedic mathematics-based algorithms are often utilized to build quick, low-power multipliers. In addition to simulation results, this section covers the four sutras of Vedic mathematics: Urdhva Tiryakbhyam, Ekadhikena Purvena, Ekanyunena Purvena, and Nikhilam. Vedic multipliers are also compared to a variety of modern multipliers, including booth, Wallace, and array multipliers. All of the sutras are evaluated according to area, speed, power, propagation delay, and mean relative error (MRE) in the current research. The results of the study will be applied in the biomedical field.