{"title":"A Novel Flat Broadband Passive Circuit with Negative Group Delay","authors":"Aixia Yuan, Niannan Chang, Junzheng Liu, Yuwei Meng","doi":"10.1007/s00034-024-02844-6","DOIUrl":null,"url":null,"abstract":"<p>A novel flat negative group delay circuit is proposed. The flatter negative group delay is achieved, and the insertion loss is reduced. The circuit structure consists of a resistor <i>R</i>1 series connected with a capacitor <i>C</i>1 and inductor <i>L</i>1 in parallel, followed by a capacitor <i>C</i>2 and inductor <i>L</i>2 in parallel, and finally connected in series with a capacitor <i>C</i>3 and inductor <i>L</i>3. The analysis design equation is provided. The effects of different component values on circuit flatness and bandwidth are analyzed. According to this design method, a flat negative group delay circuit is designed and fabricated. The simulation and measurement results are basically consistent. It has good flat negative group delay characteristics, with a group delay fluctuation of 3%, a group delay value of −1.02 ns, and an insertion loss of 7 dB. The feasibility of the design method is verified.</p>","PeriodicalId":10227,"journal":{"name":"Circuits, Systems and Signal Processing","volume":"20 1","pages":""},"PeriodicalIF":1.8000,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Circuits, Systems and Signal Processing","FirstCategoryId":"5","ListUrlMain":"https://doi.org/10.1007/s00034-024-02844-6","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
A novel flat negative group delay circuit is proposed. The flatter negative group delay is achieved, and the insertion loss is reduced. The circuit structure consists of a resistor R1 series connected with a capacitor C1 and inductor L1 in parallel, followed by a capacitor C2 and inductor L2 in parallel, and finally connected in series with a capacitor C3 and inductor L3. The analysis design equation is provided. The effects of different component values on circuit flatness and bandwidth are analyzed. According to this design method, a flat negative group delay circuit is designed and fabricated. The simulation and measurement results are basically consistent. It has good flat negative group delay characteristics, with a group delay fluctuation of 3%, a group delay value of −1.02 ns, and an insertion loss of 7 dB. The feasibility of the design method is verified.
期刊介绍：
Rapid developments in the analog and digital processing of signals for communication, control, and computer systems have made the theory of electrical circuits and signal processing a burgeoning area of research and design. The aim of Circuits, Systems, and Signal Processing (CSSP) is to help meet the needs of outlets for significant research papers and state-of-the-art review articles in the area.
The scope of the journal is broad, ranging from mathematical foundations to practical engineering design. It encompasses, but is not limited to, such topics as linear and nonlinear networks, distributed circuits and systems, multi-dimensional signals and systems, analog filters and signal processing, digital filters and signal processing, statistical signal processing, multimedia, computer aided design, graph theory, neural systems, communication circuits and systems, and VLSI signal processing.
The Editorial Board is international, and papers are welcome from throughout the world. The journal is devoted primarily to research papers, but survey, expository, and tutorial papers are also published.
Circuits, Systems, and Signal Processing (CSSP) is published twelve times annually.
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