Design of a 0.2V 2.08nW 10-bit 1kS/s High Energy Efficiency SAR ADC with Dummy Capacitor Splitting Technique for Biomedical Applications

Abstract

This paper presents an ultra-low-voltage 10-bit successive approximation-register analog-to-digital converter (SAR ADC) based on the binary search algorithm for biomedical applications. An energy-efficient DAC switching scheme for a fully differential SAR ADC is proposed, which achieves a 99.8% reduction in DAC switching energy compared to conventional SAR ADC. In this design, by using a dummy capacitor split technique, an attempt has been made to reduce the capacitor of the most significant bit, resulting in a 92.87% reduction in the total number of capacitors compared to conventional design. In the proposed structure, the common-mode voltage of the comparator is approximately constant. The maximum voltage variation in the proposed switching scheme is Vref/2. Additionally, power consumption has been reduced by implementing the power gating technique in the control logic part. The proposed converter with a sampling frequency of 1 kS/s and a supply voltage of 0.2 V has been designed and simulated in TSMC 65nm CMOS technology. Both analytical calculations and simulation results confirm the effectiveness of the proposed switching scheme. Ultimately, the proposed scheme achieves a power consumption of 2.08 nW and a Figure of Merit (FoM) of 5.39 fJ/conversion-step. In comparison with the state-of-the-art, the proposed design has demonstrated excellent performance in achieving optimal power.