Mitigating RC-Delay Induced Accuracy Loss in Analog In-Memory Computing: A Non-Compromising Approach

Abstract

The Internet of Things (IoT) has proliferated ubiquitous information exchange between the physical and cyber worlds through consumer electronics, with a focus on moving computing power to edge terminals. Computing-in-memory (CIM) technology has emerged as a competitive candidate for edge computing because of its low power consumption and high performance. In order to achieve accurate inference for neural network models, it is crucial to comprehend the source of errors in the CIM-based analog computing paradigm. In this work, we analyzed the impact of random noises and output stabling times on the Programmable Linear Random Access Memory (PLRAM)-based CIM chip. Experimental results show that the impact of random noise is negligible. The output stabling time can be treated as RC delay, which is related to the weight distribution. We proposed a weight reordering strategy to achieve better performance without sacrificing computation accuracy. Experiments with a commercial 11-keyword speech recognition model show a 74.4% runtime reduction while maintaining a 95.6% classification accuracy.