Displacement analysis in three configurations of Si0.5Ge0.5/Si junctionless gate-all-around FET: a study from device to binary and ternary circuit applications

Abstract

This article investigates the performance of a 14 nm gate length heterostructure Si_0.5Ge_0.5/Si junctionless gate-all-around (SiGe-JLGAA) device employing SILVACO ATLAS 3D simulator. The proposed device is analyzed in three configurations: underlap, fit, and overlap, and they are compared to a conventional entire region silicon JLGAA structure. First, the choice of x = 0.5 for Ge molar fraction and the device’s physical behavior for all states are discussed. Second, many analog/radio frequency (RF) figures of merit (FoMs) in terms of transconductance (g_m), gate-to-gate capacitance (C_GG), cutoff frequency (f_T), gain bandwidth product (GBP), transit time (τ), and transconductance frequency product (TFP) are investigated. The fit configuration SiGe-JLGAA device demonstrates g_m = 67.4 µS, f_T = 1033 GHz, GBP = 115 GHz, TFP = 4.2 THz/V and τ = 1.3 × 10¹³ s, whereas the corresponding values for a conventional device are 13.5 µS, 354 GHz, 37 GHz, 1.2 THz/V and 5.9 × 10¹³ s, respectively. In addition, the reliability of the proposed device in terms of linearity for the three forms is compared. Finally, using a Verilog-A model in Cadence tool, the applications of the SiGe-JLGAA device in designing two types of inverters, binary and ternary, are demonstrated. The fit form exhibits superior DC and transient characteristics compared to other structures. The proposed device significantly enhances all configurations compared to the conventional JLGAA structure, thereby opening up a wide range of applications in digital circuits.