Area and Power Modeling of Mod (\({2}^{\mathbf{n}}-\mathbf{K}\)) Adder Structure for 6-Input Lookup Table Based FPGAs

Abstract

This research article demonstrates the application of regression technique in construction of area and power estimation models for the field programmable gate array (FPGA) based implementation of modular adder. Modular adders are essential building elements of residue number system (RNS) processors. Design of Mod (\({2}^{n}-K\)) adder (\(\text{K}\in \text{I} [3, {2}^{\text{n}-1}-1]\)) discussed in this article was implemented by Ahmad Hiasat using application specific integrated circuit (ASIC) technology. The present work proposes area and power models for implementation of Hiasat’s modular adder design for FPGA device from Zynq-7000 family. Very high-speed integrated circuit hardware description language (VHDL) is used to model these designs followed by their behavioural verification using VIVADO 2014.2 tool. The proposed models are constructed using regression methodologies in MATLAB cloud based version using Curve Fit application. Accuracy of proposed models is validated against VIVADO tool.