TSTL-GNN: Graph-Based Two-Stage Transfer Learning for Timing Engineering Change Order Analysis Acceleration

Abstract

Timing Engineering Change Order (ECO) is time-consuming in IC design, requiring multiple rounds of timing analysis. Compared to traditional methods for accelerating timing analysis, which focus on a specific design, timing ECO requires higher accuracy and generalization because the design changes considerably after ECO. Additionally, there are challenges with slow acquisition of data for large designs and insufficient data for small designs. To solve these problems, we propose TSTL-GNN, a novel approach using two-stage transfer learning based on graph structures. Significantly, considering that delay calculation relies on transition time, we divide our model into two stages: the first stage predicts transition time, and the second stage predicts delay. Moreover, we employ transfer learning to transfer the model’s parameters and features from the first stage to the second due to the similar calculation formula for delay and transition time. Experiments show that our method has good accuracy on open-source and industrial applications with an average R2score/MAE of 0.9952/13.36, and performs well with data-deficient designs. Compared to previous work, our model reduce prediction errors by 37.1 ps on the modified paths, which are changed by 24.27% on average after ECO. The stable R2 score also confirms the generalization of our model. In terms of time cost, our model achieved results for path delays consuming up to 80 times less time compared to open-source tool.