A novel SiC VD-MOSFET with optimized P-type shielding structure in JFET region for improved short circuit robustness

Abstract

This paper investigates the short-circuit characteristics of Silicon Carbide (SiC) Vertical Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor (VD-MOSFET) utilizing TCAD tools. Expanding upon the conventional VD-MOSFET framework, a novel 900V SiC VD-MOSFET with two P-type shielding layer introduced in JFET region, PW-MOSFET, is proposed and designed. In contrast to the traditional VD MOSFET, PW- -MOSFET not only significantly improves short-circuit (SC) reliability but also optimizes static performance. Simulation results reveal that PW-MOSFET demonstrates notably superior SC performance at a DC link voltage of 600V compared to the traditional VD-MOSFET, with a 63% increase in Short-Circuit Withstand Time (SCWT) and a 25% enhancement in Baliga Figure of Merit (FOM). The key factor contributing to this performance enhancement is attributed to the advantageous role of the P-type shielding layer, facilitating adjustments in the current flow path, thereby suppressing saturation current and enhancing the reliability of short-circuit events. Furthermore, the issue of increased characteristic on-state resistance (Ron, sp) resulting from the introduction of the P-type shielding layer is addressed by augmenting the doping concentration in the JFET region.