Review of chiplet-based design: system architecture and interconnection

Abstract

Chiplet-based design, which breaks a system into multiple smaller dice (or “chiplets”) and reassembles them into a new system chip through advanced packaging, has received extensive attention in the post Moore’s law era due to its advantages in terms of cost, performance, and agility. However, significant challenges arise in this implementation approach, including the mapping of functional components onto chiplets, co-optimization of package and architecture, handling the increased latency of communication across functions in different dies, the uncertainty problems of fragment communication subsystems, such as maintaining deadlock-free when independently designed chiplets are combined. Despite various design approaches that attempt to address these challenges, surveying these approaches one-after-another is not the most helpful way to offer a comparative viewpoint. Accordingly, in this paper, we present a more comprehensive and systematic strategy to survey the various approaches. First, we divide them into chiplet-based system architecture design and interconnection design, and further classify them based on different architectures and building blocks of interconnection. Then, we analyze and cross-compare each classification separately, and in addition, we present a topical discussion on the evolution of memory architectures, design automation, and other relevant topics in chiplet-based designs. Finally, some discussions on important topics are presented, emphasizing future needs and challenges in this rapidly evolving field.