APPAs: fast and efficient approximate parallel prefix adders and multipliers

Abstract

In this paper, the approximate parallel prefix adders with minimizing hardware and timing complexities are proposed. Moreover, an approximate multiplier based on these adders is designed. The approximate structures include two approximate Sklansky adders, one approximate Ladner-Fischer adder, and one approximate Kogge-Stone adder. The proposed adders are free from carry rippling. The main strategy for approximate design is primarily based on rearranging and deleting sub-blocks and secondary reducing the critical path delay and area in the adders. In this case, we have a trade-off between accuracy, delay, and area. The proposed approximate multiplier has a serial structure that is designed based on using one approximate parallel prefix adder. The proposed approximate adders and multiplier are compared from hardware and accuracy point of view such as gate count, delay, area delay product, error rate, mean error distance, mean relative error distance, and normalized error distance. The efficacy of proposed structures in image processing applications such as image smoothing (low-pass filter) and image multiplication is performed using MATLAB. The results show the proposed approximate structures are comparable in terms of area, delay, PSNR, and mean structural similarity index metric parameters with other works.