{"title":"Single-Rating Multilevel Current Source Inverter With Fault Tolerance","authors":"Faramarz Faraji;Honnyong Cha","doi":"10.1109/JESTPE.2024.3432888","DOIUrl":null,"url":null,"abstract":"The paralleled H-bridge multilevel current source inverter (PHB-MLCSI) provides a practical means to enhance both the system’s current rating and power quality simultaneously. Even so, challenges such as separate dc sources and the need for bulky input dc inductors present notable obstacles in the PHB-MLCSI with an independent dc-link configuration, potentially increasing the system’s cost and size. The PHB-MLCSI with a shared dc-link, also known as the single-rating MLCSI (SR-MLCSI), can overcome these limitations. However, the SR-MLCSI faces the issue of open-circuit fault (OCF), similar to other traditional CSIs. Recently, a topology known as paralleled H-bridge multilevel switching-cell current source inverter (PHB-MLSC2SI) has been proposed in the literature to address the OCF issue in conventional PHB-MLCSI. However, this topology retains the same limitations as those mentioned for PHB-MLCSI. This article proposes a modified version of SR-MLCSI, termed SR-MLCSI with fault tolerance (SR-MLCSIFT), to address the OCF issue in SR-MLCSI and mitigate the size, weight, cost, and complexity drawbacks of PHB-MLCSI and PHB-MLSC2SI. Additionally, the article investigates several extremely severe faulty scenarios for the first time within the proposed topology. A detailed operational principle of the suggested inverter under OCF conditions is provided, accompanied by a comprehensive comparison with several MLCSI counterparts. Extensive experimental tests are conducted to validate the effectiveness of the proposed solution.","PeriodicalId":13093,"journal":{"name":"IEEE Journal of Emerging and Selected Topics in Power Electronics","volume":null,"pages":null},"PeriodicalIF":4.6000,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Emerging and Selected Topics in Power Electronics","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10608052/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
The paralleled H-bridge multilevel current source inverter (PHB-MLCSI) provides a practical means to enhance both the system’s current rating and power quality simultaneously. Even so, challenges such as separate dc sources and the need for bulky input dc inductors present notable obstacles in the PHB-MLCSI with an independent dc-link configuration, potentially increasing the system’s cost and size. The PHB-MLCSI with a shared dc-link, also known as the single-rating MLCSI (SR-MLCSI), can overcome these limitations. However, the SR-MLCSI faces the issue of open-circuit fault (OCF), similar to other traditional CSIs. Recently, a topology known as paralleled H-bridge multilevel switching-cell current source inverter (PHB-MLSC2SI) has been proposed in the literature to address the OCF issue in conventional PHB-MLCSI. However, this topology retains the same limitations as those mentioned for PHB-MLCSI. This article proposes a modified version of SR-MLCSI, termed SR-MLCSI with fault tolerance (SR-MLCSIFT), to address the OCF issue in SR-MLCSI and mitigate the size, weight, cost, and complexity drawbacks of PHB-MLCSI and PHB-MLSC2SI. Additionally, the article investigates several extremely severe faulty scenarios for the first time within the proposed topology. A detailed operational principle of the suggested inverter under OCF conditions is provided, accompanied by a comprehensive comparison with several MLCSI counterparts. Extensive experimental tests are conducted to validate the effectiveness of the proposed solution.
期刊介绍:
The aim of the journal is to enable the power electronics community to address the emerging and selected topics in power electronics in an agile fashion. It is a forum where multidisciplinary and discriminating technologies and applications are discussed by and for both practitioners and researchers on timely topics in power electronics from components to systems.