MP-ORAM: A Novel ORAM Design for Multicore Processor Systems

IF 7 2区 计算机科学 Q1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Sajid Hussain, Hui Guo, Tuo Li, Sri Parameswaran
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引用次数: 0

Abstract

Security becomes increasingly critical in today's ubiquitous computing. One vulnerable part of a computing system is the bus between the processor chip and the external off-chip memory, where data transferred on the bus can be snooped. To protect data confidentiality, encryption is commonly used. However, encryption alone is not sufficient since the adversary can still find out useful information using the memory address trace. Oblivious RAM (ORAM) is a strong security measure to prevent such information leak. ORAM hides a true memory access in a round of random (dummy) accesses to the memory such that the data and addresses transferred over the memory buses look oblivious to the adversary. However, the existing ORAM designs often incur a hefty performance overhead, which greatly slows down the processor execution, especially for the multicore processor system where the potentially high memory access frequency from the multiple cores could make the impact of the performance overhead even more critical. To address this issue, we, for the first time, propose to process multiple memory access requests in a single round of dummy memory accesses. As such, we develop a novel ORAM design, called MP-ORAM, that targets the multicore system and is able to simultaneously handle a dynamic number of memory access requests to mitigate the performance overhead without compromising the obliviousness of the off-chip memory access trace. We have built a prototype for MP-ORAM and successfully integrated it into a RISCV-based multicore processor system. The whole system has also been implemented on a Xilinx Ultrascale+ ZCU102 FPGA board, with which we can effectively evaluate the performance of our design. Our evaluation, based on the SPLASH-2 benchmark suit, shows that MP-ORAM improves performance by 51–157% while only consuming up to 22% extra FPGA resources as compared to the baseline design. Furthermore, from the NIST randomness tests on the memory access traces generated by MP-ORAM, we have demonstrated that this performance improvement does not affect the obliviousness of the memory access trace. Most importantly, MP-ORAM is the first ORAM design of its kind that has been fully implemented and evaluated on a real multicore processor system with OS support.
MP-ORAM:适用于多核处理器系统的新型 ORAM 设计
在当今无所不在的计算领域,安全变得越来越重要。计算系统中一个易受攻击的部分是处理器芯片与外部片外存储器之间的总线,总线上传输的数据可能被窥探。为了保护数据的机密性,通常会使用加密技术。然而,仅仅加密是不够的,因为对手仍然可以利用内存地址跟踪找出有用的信息。遗忘内存(ORAM)是防止此类信息泄露的有力安全措施。ORAM 将真正的内存访问隐藏在对内存的一轮随机(虚假)访问中,这样,通过内存总线传输的数据和地址在对手看来是可忽略的。然而,现有的 ORAM 设计通常会产生巨大的性能开销,从而大大降低处理器的执行速度,特别是在多核处理器系统中,多个内核可能产生的高内存访问频率会使性能开销的影响变得更加严重。为了解决这个问题,我们首次提出在一轮虚拟内存访问中处理多个内存访问请求。因此,我们开发了一种名为 MP-ORAM 的新型 ORAM 设计,它以多核系统为目标,能够同时处理动态数量的内存访问请求,从而在不影响片外内存访问轨迹的遗忘性的情况下减轻性能开销。我们建立了 MP-ORAM 的原型,并成功地将其集成到基于 RISCV 的多核处理器系统中。我们还在 Xilinx Ultrascale+ ZCU102 FPGA 板上实现了整个系统,从而可以有效评估我们设计的性能。基于 SPLASH-2 基准服的评估结果表明,MP-ORAM 与基准设计相比,性能提高了 51-157%,而额外消耗的 FPGA 资源最多只有 22%。此外,通过对 MP-ORAM 生成的内存访问轨迹进行 NIST 随机性测试,我们证明这种性能改进不会影响内存访问轨迹的遗忘性。最重要的是,MP-ORAM 是首个在支持操作系统的真实多核处理器系统上全面实施和评估的同类 ORAM 设计。
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来源期刊
IEEE Transactions on Dependable and Secure Computing
IEEE Transactions on Dependable and Secure Computing 工程技术-计算机:软件工程
CiteScore
11.20
自引率
5.50%
发文量
354
审稿时长
9 months
期刊介绍: The "IEEE Transactions on Dependable and Secure Computing (TDSC)" is a prestigious journal that publishes high-quality, peer-reviewed research in the field of computer science, specifically targeting the development of dependable and secure computing systems and networks. This journal is dedicated to exploring the fundamental principles, methodologies, and mechanisms that enable the design, modeling, and evaluation of systems that meet the required levels of reliability, security, and performance. The scope of TDSC includes research on measurement, modeling, and simulation techniques that contribute to the understanding and improvement of system performance under various constraints. It also covers the foundations necessary for the joint evaluation, verification, and design of systems that balance performance, security, and dependability. By publishing archival research results, TDSC aims to provide a valuable resource for researchers, engineers, and practitioners working in the areas of cybersecurity, fault tolerance, and system reliability. The journal's focus on cutting-edge research ensures that it remains at the forefront of advancements in the field, promoting the development of technologies that are critical for the functioning of modern, complex systems.
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