A Computation of the Ninth Dedekind Number using FPGA Supercomputing

ACM Transactions on Reconfigurable Technology and Systems Pub Date : 2024-07-02 DOI:10.1145/3674147

Lennart Van Hirtum, P. D. Causmaecker, Jens Goemaere, Tobias Kenter, Heinrich Riebler, Michael Lass, Christian Plessl

引用次数: 0

Abstract

This manuscript makes the claim of having computed the \(9^{th}\) Dedekind number, D(9). This was done by accelerating the core operation of the process with an efficient FPGA design that outperforms an optimized 64-core CPU reference by 95 \(\times\) . The FPGA execution was parallelized on the Noctua 2 supercomputer at Paderborn University. The resulting value for D(9) is \(286386577668298411128469151667598498812366\) . This value can be verified in two steps. We have made the data file containing the 490M results available, each of which can be verified separately on CPU, and the whole file sums to our proposed value. The paper explains the mathematical approach in the first part, before putting the focus on a deep dive into the FPGA accelerator implementation followed by a performance analysis. The FPGA implementation was done in RTL using a dual-clock architecture and shows how we achieved an impressive FMax of 450MHz on the targeted Stratix 10 GX 2800 FPGAs. The total compute time used was 47’000 FPGA Hours.

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利用 FPGA 超级计算计算第九代德金数

本手稿宣称已经计算出了（9^{th}\）Dedekind数D(9)。这是通过使用高效的FPGA设计加速过程的核心操作实现的，其性能比优化的64核CPU基准高出95 \ (\次\)。FPGA 的执行在帕德博恩大学的 Noctua 2 超级计算机上并行进行。由此得出的 D(9) 值为 286386577668298411128469151667598498812366\) 。这个值可以通过两个步骤来验证。我们提供了包含 490M 结果的数据文件，每个结果都可以在 CPU 上单独验证，整个文件的总和就是我们提出的值。本文在第一部分解释了数学方法，然后重点深入探讨了 FPGA 加速器的实现，并进行了性能分析。FPGA 的实现是在 RTL 中使用双时钟架构完成的，并展示了我们如何在目标 Stratix 10 GX 2800 FPGA 上实现 450MHz 的惊人 FMax。使用的总计算时间为 47,000 FPGA 小时。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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ACM Transactions on Reconfigurable Technology and Systems

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