Hardware software SoC co-design analysis and implementation of MIMO-OFDM for 4G/5G/6G eNodeB applications

IF 2.5 4区 计算机科学 Q3 TELECOMMUNICATIONS
Sanket N. Dessai, Hemant Patidar
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引用次数: 0

Abstract

With the emerging challenges for the data rate requirements of 5G/6G applications and reusing the 4G infrastructure for 5G, it is necessary to understand the System-on-Chip (SoC) platform-based embedded co-design and implementation of the programmable and reconfigurable MIMO-OFDM system. For both uplink and downlink data transmissions, these applications require a larger data throughput as well as reduced bit error rates, latency, and increased spectral efficiency. This work describes the co-design and development of hardware and software for the MIMO-OFDM algorithms for 5G and 6G eNodeBs. An efficient design through computer architecture based on pipeline and parallelization using systolic and CORDIC has been applied for the IP development of the sub-components of the MIMO-OFDM systems. A Zynq platform with computing resources including PS, Mali GPU-400, and PL is utilized to increase the data rate for MIMO-OFDM system architecture co-design and implementation. The architecture approach used in this work enabled a data rate of 10–50 Gbps and beyond reaching Tbps based on the system's programmability and reconfigurability with an efficient SoC platform design. The design platform provides a programming feature such as MIMO-OFDM, OFDM, and MIMO without OFDM through software programming for the range of applications of the desired data rates. With 64-QAM modulation, the three channels' observed performance in the predicted multipath channel velocity of 15 km/h for pedestrians, vehicles, and AWGN is seen in simulation. To reach the application clock frequencies, the device's PLL (ZUI7EG) upscales and downscales clock frequencies from 750 to 1600 MHz using a configurable register. When the system is configured to operate as MIMO-OFDM or OFDM in order to get an execution throughput of 300 msec and a data throughput ranging from 71 Gbps to 1749 Gbps using 2 × 2/4 × 4 configurations. The device scalability depends on at present devices of advanced embedded reconfigurable architecture platform. Massive MIMO and multi-user MIMO will be used in the future to increase throughput and data rates. Additionally, future work will focus on creating a MIMO-OFDM hardware-software embedded architecture and testbed to enhance implementation and verification of the vehicle and pedestrian.

面向 4G/5G/6G eNodeB 应用的 MIMO-OFDM 硬件软件 SoC 协同设计分析与实施
随着 5G/6G 应用对数据传输速率的要求以及为 5G 重复使用 4G 基础设施所带来的新挑战,有必要了解基于片上系统(SoC)平台的嵌入式协同设计以及可编程和可重构 MIMO-OFDM 系统的实现。对于上行和下行数据传输,这些应用需要更大的数据吞吐量、更低的误码率、更短的延迟和更高的频谱效率。本研究介绍了针对 5G 和 6G eNodeB 的 MIMO-OFDM 算法的硬件和软件的共同设计和开发。在 MIMO-OFDM 系统子组件的 IP 开发中,采用了基于流水线和并行化的高效计算机架构设计,并使用了系统和 CORDIC。利用 Zynq 平台的计算资源(包括 PS、Mali GPU-400 和 PL)提高了 MIMO-OFDM 系统架构协同设计和实施的数据速率。基于系统的可编程性和可重构性以及高效的 SoC 平台设计,这项工作中使用的架构方法使数据传输率达到 10-50 Gbps,甚至超过 Tbps。设计平台通过软件编程提供了 MIMO-OFDM、OFDM 和 MIMO(无 OFDM)等编程功能,以满足所需数据传输速率的应用范围。在 64-QAM 调制下,通过仿真可以观察到三个信道在行人、车辆和 AWGN 的多径信道速度为 15 km/h 时的表现。为了达到应用时钟频率,该器件的 PLL (ZUI7EG) 通过一个可配置寄存器将时钟频率从 750 MHz 升频或降频至 1600 MHz。系统配置为 MIMO-OFDM 或 OFDM 时,执行吞吐量为 300 毫秒,数据吞吐量为 71 Gbps 至 1749 Gbps(采用 2 × 2/4 × 4 配置)。设备的可扩展性取决于目前先进的嵌入式可重构架构平台的设备。未来将使用大规模多输入多输出(MIMO)和多用户多输入多输出(MIMO)来提高吞吐量和数据传输速率。此外,未来的工作将侧重于创建 MIMO-OFDM 硬件-软件嵌入式架构和测试平台,以加强车辆和行人的实施和验证。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
CiteScore
8.90
自引率
13.90%
发文量
249
期刊介绍: ransactions on Emerging Telecommunications Technologies (ETT), formerly known as European Transactions on Telecommunications (ETT), has the following aims: - to attract cutting-edge publications from leading researchers and research groups around the world - to become a highly cited source of timely research findings in emerging fields of telecommunications - to limit revision and publication cycles to a few months and thus significantly increase attractiveness to publish - to become the leading journal for publishing the latest developments in telecommunications
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