GoPlace: chip placement like playing go

Abstract

As a critical stage in modern Very-Large-Scale Integrated (VLSI) design, placement plays a crucial role in positioning numerous circuit modules of varying sizes onto a 2D chip canvas to achieve optimal performance. In recent years, applying machine learning methods to placement has emerged as a promising solution for significantly enhancing efficiency and achieving superior results. However, machine learning-driven methods are still in their early stages, facing challenges such as exploration and convergence difficulties. In addition, it is challenging to integrate netlist data with the placement information. This paper proposes a novel approach leveraging deep reinforcement learning to address these challenges. First, a multi-layer chip canvas state representation method is proposed to tackle the challenges of storing and using the placement information. Additionally, a graph neural network is used to assist in generating placement information. Second, this paper proposed a semi-shared policy and value network, and to accommodate the scale and complexity of chip placement, a residual-like neural network is proposed. Third, extensive experiments on eight circuits of public benchmarks show that GoPlace achieves 10% ~ 25% wirelength reduction compared to other reinforcement learning-based methods, lowest congestion, and guarantees zero overlap.