SoC-FPGA Based Concept of Hardware Aided Quantum Simulation

Q4 Engineering
Jacek Długopolski, Jakub Czerski, Mateusz Knapik
{"title":"SoC-FPGA Based Concept of Hardware Aided Quantum Simulation","authors":"Jacek Długopolski, Jakub Czerski, Mateusz Knapik","doi":"10.14313/jamris/2-2024/9","DOIUrl":null,"url":null,"abstract":"Contemporary industry and science expectations towards technological solutions set the bar high. Current approaches to increasing the computing power of standard systems are reaching the limits of physics known to humankind. Fast, programmable systems with relatively low power consumption are a different concept for performing complex calculations. Highly parallel processing opens up a number of possibilities in the context of accelerating calculations. Application of SoC (System On Chip) with FPGA (Field-Programmable Gate Array) enables to delegate of a part of computations to the gates matrix, thereby expediting processing by using parallelization of hardware operations. This paper presents the general concept of using SoC FPGA systems to support CPU (Central Processing Unit) in many modern tasks. While some tasks might be really hard to implement on an FPGA in a reasonable time, the SoC FPGA platform allows for easy low-level interconnections, and with such virtualized access to the hardware computing resources, it is seen as making FPGAs, or hardware in general, more accessible to engineers accustomed to high-level solutions. The concept presented in the article takes into account the limited resources of cheaper educational platforms, which, however, still provide an interesting and alternative hybrid solution to the problem of parallelization and acceleration of data processing. This allows to overcome encountered limitations and maintain the flexibility known from high-level solutions and high performance achieved with low-level programming, without the need for a high financial background.","PeriodicalId":37910,"journal":{"name":"Journal of Automation, Mobile Robotics and Intelligent Systems","volume":"75 7","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2024-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Automation, Mobile Robotics and Intelligent Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.14313/jamris/2-2024/9","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"Engineering","Score":null,"Total":0}
引用次数: 0

Abstract

Contemporary industry and science expectations towards technological solutions set the bar high. Current approaches to increasing the computing power of standard systems are reaching the limits of physics known to humankind. Fast, programmable systems with relatively low power consumption are a different concept for performing complex calculations. Highly parallel processing opens up a number of possibilities in the context of accelerating calculations. Application of SoC (System On Chip) with FPGA (Field-Programmable Gate Array) enables to delegate of a part of computations to the gates matrix, thereby expediting processing by using parallelization of hardware operations. This paper presents the general concept of using SoC FPGA systems to support CPU (Central Processing Unit) in many modern tasks. While some tasks might be really hard to implement on an FPGA in a reasonable time, the SoC FPGA platform allows for easy low-level interconnections, and with such virtualized access to the hardware computing resources, it is seen as making FPGAs, or hardware in general, more accessible to engineers accustomed to high-level solutions. The concept presented in the article takes into account the limited resources of cheaper educational platforms, which, however, still provide an interesting and alternative hybrid solution to the problem of parallelization and acceleration of data processing. This allows to overcome encountered limitations and maintain the flexibility known from high-level solutions and high performance achieved with low-level programming, without the need for a high financial background.
基于 SoC-FPGA 的硬件辅助量子模拟概念
当代工业和科学界对技术解决方案的期望设定了很高的标准。目前提高标准系统计算能力的方法已达到人类已知物理学的极限。快速、可编程、功耗相对较低的系统是进行复杂计算的另一个概念。高度并行处理为加速计算提供了多种可能性。通过应用带有 FPGA(现场可编程门阵列)的 SoC(片上系统),可以将部分计算委托给门矩阵,从而利用硬件操作的并行化加快处理速度。本文介绍了在许多现代任务中使用 SoC FPGA 系统来支持 CPU(中央处理器)的一般概念。虽然有些任务可能确实难以在合理的时间内在 FPGA 上实现,但 SoC FPGA 平台允许轻松实现底层互连,而且通过这种对硬件计算资源的虚拟化访问,FPGA 或一般硬件更容易为习惯于高层解决方案的工程师所使用。文章中提出的概念考虑到了廉价教育平台的有限资源,但仍为数据处理的并行化和加速问题提供了一种有趣的替代性混合解决方案。这样就能克服遇到的限制,保持高级解决方案的灵活性和低级编程的高性能,而不需要很高的资金背景。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
Journal of Automation, Mobile Robotics and Intelligent Systems
Journal of Automation, Mobile Robotics and Intelligent Systems Engineering-Control and Systems Engineering
CiteScore
1.10
自引率
0.00%
发文量
25
期刊介绍: Fundamentals of automation and robotics Applied automatics Mobile robots control Distributed systems Navigation Mechatronics systems in robotics Sensors and actuators Data transmission Biomechatronics Mobile computing
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信