Low static power consumption GaN-based CMOS-like inverter design

Abstract

It is necessary to achieve current matching for GaN-based CMOS-like inverters. However, due to the low hole mobility of GaN p-FET devices, the weak output capacity of GaN p-FET devices makes it difficult to obtain current matching with n-FET devices in the off-state, which hinders the development of GaN-based CMOS-like inverters. In this study, a GaN-based CMOS-like device with an AlGaN back barrier layer is designed and its off-state leakage current is compared with that without an AlGaN back-barrier layer. The results show that the 2DEG confinement in the GaN-based n-FET device with an AlGaN back barrier layer can be enhanced and the leakage current is reduced from 10^–3 A to 10^–6 A in the off-state. This is accomplished without influencing the current of the GaN-based p-FET device in the off-state, resulting in a good current consistency between the n-FET device and the p-FET device in the off-state. The static power consumption is 4.5 µW for GaN-based CMOS-like inverters with an AlGaN back barrier structure when it is operated at V_dd = 5 V. The rise time (t_r) and fall time (t_f) of the GaN-based CMOS-like inverters are 4 μs and 0.12 μs, respectively. The low noise margin (NM_L) is 1.90 V and the high noise margin (NM_H) is 2.55 V. This work lays a foundation for the development of the future of GaN-based integrated ICs.