Performance Analysis of Approximate Parallel Prefix Adders Realized with Field-programmable Gate Array Technology

Abstract

Parallel prefix adders are widely used in high-speed arithmetic circuits due to their ability to perform additions in logarithmic time. However, the high area and delay of exact parallel prefix adders prompted the development of approximate parallel prefix adders. These adders are a promising solution for high-speed arithmetic circuits because they sacrifice accuracy for reduced area and delay. This paper presents a performance analysis of five approximate parallel prefix adders realized with field programmable gate array technology. The five approximate parallel prefix adders are the Kogge-Stone adder, the Sklansky adder, the Brent-Kung adder, the Han-Carlson adder, and the Ladner-Fisher. Each adder is implemented in a Xilinx Artix-7 FPGA. The area and delay of five approximate parallel prefix adders are evaluated. The Kogge-Stone approximate parallel prefix adder, out of five approximate parallel prefix adders, consumes the least delay, irrespective of the number of bits. The Sklansky approximate parallel prefix adder out of five approximate parallel prefix adders consumes the least area irrespective of the number of bits in addition. Overall, our research sheds light on the trade-offs between area, power delay, and power delay products of five approximate parallel prefix adders implemented with FPGA technology. This analysis can help choose the best approximate parallel prefix adder for specific high-speed arithmetic applications. In the case of 16- and 32-bit five approximate parallel prefix adders, Ladner-fisher shows the best power delay product, whereas 64- and 128-bit five approximate parallel prefix adders, Sklansky adder shows the best power delay product.