Dynamic-ACTS - A Dynamic Graph Analytics Accelerator For HBM-Enabled FPGAs

IF 3.1 4区计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

ACM Transactions on Reconfigurable Technology and Systems Pub Date : 2024-04-30 DOI:10.1145/3662002

Oluwole Jaiyeoba, Kevin Skadron

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引用次数: 0

Abstract

Graph processing frameworks suffer performance degradation from under-utilization of available memory bandwidth, because graph traversal often exhibits poor locality. A prior work, ACTS [24], accelerates graph processing with FPGAs and High Bandwidth Memory (HBM). ACTS achieves locality by partitioning vertex-update messages (based on destination vertex IDs) generated online after active edges have been processed. This work introduces Dynamic-ACTS which builds on ideas in ACTS to support dynamic graphs. The key innovation is to use a hash table to find the edges to be updated. Compared to Gunrock, a GPU graph engine, Dynamic-ACTS achieves a geometric mean speedup of 1.5X, with a maximum speedup of 4.6X. Compared to GraphLily, an FPGA-HBM graph engine, Dynamic-ACTS achieves a geometric speedup of 3.6X, with a maximum speedup of 16.5X. Our results also showed a geometric mean power reduction of 50% and a mean reduction of energy-delay product of 88% over Gunrock. Compared to GraSU, an FPGA graph updating engine, Dynamic-ACTS achieves an average speedup of 15X.

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Dynamic-ACTS - 面向 HBM FPGA 的动态图形分析加速器

由于图形遍历通常表现出较低的局部性，可用内存带宽利用不足导致图形处理框架性能下降。之前的一项研究成果 ACTS [24]，利用 FPGA 和高带宽内存（HBM）加速了图形处理。ACTS 通过分割活动边处理后在线生成的顶点更新信息（基于目标顶点 ID）来实现局部性。这项工作引入了 Dynamic-ACTS，它以 ACTS 的理念为基础，支持动态图。其主要创新在于使用哈希表来查找要更新的边。与 GPU 图形引擎 Gunrock 相比，Dynamic-ACTS 的几何平均速度提高了 1.5 倍，最大速度提高了 4.6 倍。与 FPGA-HBM 图形引擎 GraphLily 相比，Dynamic-ACTS 的几何平均速度提高了 3.6 倍，最大速度提高了 16.5 倍。我们的结果还显示，与 Gunrock 相比，几何平均功耗降低了 50%，能耗-延迟乘积平均降低了 88%。与 FPGA 图形更新引擎 GraSU 相比，Dynamic-ACTS 的平均速度提高了 15 倍。

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来源期刊

ACM Transactions on Reconfigurable Technology and Systems COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.90

自引率

8.70%

发文量

审稿时长

>12 weeks

期刊介绍： TRETS is the top journal focusing on research in, on, and with reconfigurable systems and on their underlying technology. The scope, rationale, and coverage by other journals are often limited to particular aspects of reconfigurable technology or reconfigurable systems. TRETS is a journal that covers reconfigurability in its own right. Topics that would be appropriate for TRETS would include all levels of reconfigurable system abstractions and all aspects of reconfigurable technology including platforms, programming environments and application successes that support these systems for computing or other applications. -The board and systems architectures of a reconfigurable platform. -Programming environments of reconfigurable systems, especially those designed for use with reconfigurable systems that will lead to increased programmer productivity. -Languages and compilers for reconfigurable systems. -Logic synthesis and related tools, as they relate to reconfigurable systems. -Applications on which success can be demonstrated. The underlying technology from which reconfigurable systems are developed. (Currently this technology is that of FPGAs, but research on the nature and use of follow-on technologies is appropriate for TRETS.) In considering whether a paper is suitable for TRETS, the foremost question should be whether reconfigurability has been essential to success. Topics such as architecture, programming languages, compilers, and environments, logic synthesis, and high performance applications are all suitable if the context is appropriate. For example, an architecture for an embedded application that happens to use FPGAs is not necessarily suitable for TRETS, but an architecture using FPGAs for which the reconfigurability of the FPGAs is an inherent part of the specifications (perhaps due to a need for re-use on multiple applications) would be appropriate for TRETS.