The CMOS Pseudo-Thyristor: a zero-static current discriminator circuit

X. Wen, T. Fu, D. Gong, X. Huang, T. Liu, P. Gui, J. Wu
{"title":"The CMOS Pseudo-Thyristor: a zero-static current discriminator circuit","authors":"X. Wen, T. Fu, D. Gong, X. Huang, T. Liu, P. Gui, J. Wu","doi":"10.1088/1748-0221/19/04/c04034","DOIUrl":null,"url":null,"abstract":"\n A very low power discriminator circuit for pixelized detectors, called the Pseudo-Thyristor is described in this document. It is a positive feedback topology using regular PMOS and NMOS field-effect transistors (FET's) with zero static current. When a small charge is injected into the circuit, it flips rapidly due to the positive feedback and outputs a logic transition for further digitization. Simulation shows that in a 65 nm process, it is possible to achieve a detecting threshold below 5 fC while maintain the average power consumption below 10 micro-Watts when the hit occupancy is <10% for 40 MHz operation.","PeriodicalId":507814,"journal":{"name":"Journal of Instrumentation","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2024-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Instrumentation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1088/1748-0221/19/04/c04034","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

A very low power discriminator circuit for pixelized detectors, called the Pseudo-Thyristor is described in this document. It is a positive feedback topology using regular PMOS and NMOS field-effect transistors (FET's) with zero static current. When a small charge is injected into the circuit, it flips rapidly due to the positive feedback and outputs a logic transition for further digitization. Simulation shows that in a 65 nm process, it is possible to achieve a detecting threshold below 5 fC while maintain the average power consumption below 10 micro-Watts when the hit occupancy is <10% for 40 MHz operation.
CMOS 伪晶闸管:零静态电流鉴别器电路
本文件介绍了一种用于像素化检测器的超低功耗鉴别电路,称为伪晶闸管(Pseudo-Thyristor)。它是一种正反馈拓扑结构,使用常规的 PMOS 和 NMOS 场效应晶体管(FET),静态电流为零。当向电路中注入少量电荷时,由于正反馈作用,电路会迅速翻转,并输出逻辑转换,以便进一步数字化。仿真结果表明,在 65 纳米工艺中,可以实现低于 5 fC 的检测阈值,同时在 40 MHz 工作频率下,当命中率小于 10% 时,平均功耗保持在 10 微瓦以下。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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