{"title":"Data transmission architecture of the ALICE ITS3 stitched sensor prototype MOSAIX","authors":"P. Dorosz","doi":"10.1088/1748-0221/19/04/c04050","DOIUrl":null,"url":null,"abstract":"\n The ALICE Collaboration will replace the three innermost layers of the Inner Tracker\n System (ITS) at the LHC with an innovative vertex detector. A single-die stitched monolithic pixel\n detector segment of 1.85 cm × 26.6 cm designed in 65 nm CMOS imaging technology will be\n used as a building block for these layers. The pixel detector segment consists of 144 data\n transmitters that are evenly distributed over the full area. The data communication is done via\n the 1.85 cm short edge of the detector. This contribution will focus on the architecture,\n challenges, and techniques used to aggregate up to 30.72 Gb/s of data flux arriving at the short\n edge of the chip and to send it off-chip.","PeriodicalId":507814,"journal":{"name":"Journal of Instrumentation","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2024-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Instrumentation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1088/1748-0221/19/04/c04050","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The ALICE Collaboration will replace the three innermost layers of the Inner Tracker
System (ITS) at the LHC with an innovative vertex detector. A single-die stitched monolithic pixel
detector segment of 1.85 cm × 26.6 cm designed in 65 nm CMOS imaging technology will be
used as a building block for these layers. The pixel detector segment consists of 144 data
transmitters that are evenly distributed over the full area. The data communication is done via
the 1.85 cm short edge of the detector. This contribution will focus on the architecture,
challenges, and techniques used to aggregate up to 30.72 Gb/s of data flux arriving at the short
edge of the chip and to send it off-chip.