R. Manera, R. Ballabriga, J. Mauricio, J. Kaplon, A. Paternò, F. Bandi, S. Gómez, A. Pulli, S. Portero, J. Silva, F. Keizer, C. D’Ambrosio, M. Campbell, D. Gascón
{"title":"The analog front end for FastRICH: an ASIC for the LHCb RICH detector upgrade","authors":"R. Manera, R. Ballabriga, J. Mauricio, J. Kaplon, A. Paternò, F. Bandi, S. Gómez, A. Pulli, S. Portero, J. Silva, F. Keizer, C. D’Ambrosio, M. Campbell, D. Gascón","doi":"10.1088/1748-0221/19/04/c04030","DOIUrl":null,"url":null,"abstract":"\n This work presents the analog circuitry of the FastRICH ASIC, a 16-channel ASIC, developed\n in a 65 nm CMOS technology specifically designed for the RICH detector at LHCb to readout\n detectors like Photomultiplier Tubes to be used at the LHC Run 4 and Silicon Photomultipliers\n candidates for Run 5. The front-end (FE) stage has an input impedance below 50 Ω and an\n input dynamic range from 5 μA to 5 mA with a power consumption of ∼5 mW/channel. The chip\n includes a Leading Edge Comparator (LED) and a Constant Fraction Discriminator (CFD) for time\n pick-off and a Time-to-Digital Converter (TDC) for digitization.","PeriodicalId":507814,"journal":{"name":"Journal of Instrumentation","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2024-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Instrumentation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1088/1748-0221/19/04/c04030","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This work presents the analog circuitry of the FastRICH ASIC, a 16-channel ASIC, developed
in a 65 nm CMOS technology specifically designed for the RICH detector at LHCb to readout
detectors like Photomultiplier Tubes to be used at the LHC Run 4 and Silicon Photomultipliers
candidates for Run 5. The front-end (FE) stage has an input impedance below 50 Ω and an
input dynamic range from 5 μA to 5 mA with a power consumption of ∼5 mW/channel. The chip
includes a Leading Edge Comparator (LED) and a Constant Fraction Discriminator (CFD) for time
pick-off and a Time-to-Digital Converter (TDC) for digitization.