Nan Wu, Yingjie Li, Hang Yang, Hanqiu Chen, Steve Dai, Cong Hao, Cunxi Yu, Yuan Xie
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引用次数: 0
Abstract
With the ever-increasing hardware design complexity comes the realization that efforts required for hardware verification increase at an even faster rate. Driven by the push from the desired verification productivity boost and the pull from leap-ahead capabilities of machine learning (ML), recent years have witnessed the emergence of exploiting ML-based techniques to improve the efficiency of hardware verification. In this paper, we present a panoramic view of how ML-based techniques are embraced in hardware design verification, from formal verification to simulation-based verification, from academia to industry, and from current progress to future prospects. We envision that the adoption of ML-based techniques will pave the road for more scalable, more intelligent, and more productive hardware verification.
随着硬件设计复杂性的不断增加,人们意识到硬件验证所需的工作量也在以更快的速度增加。在希望提高验证生产率的推动下,以及机器学习(ML)飞跃能力的拉动下,近年来出现了利用基于 ML 的技术来提高硬件验证效率的趋势。在本文中,我们从形式验证到基于仿真的验证,从学术界到工业界,从当前进展到未来展望,全景展示了基于 ML 的技术在硬件设计验证中的应用。我们设想,基于 ML 的技术的采用将为更可扩展、更智能和更高效的硬件验证铺平道路。
期刊介绍:
TODAES is a premier ACM journal in design and automation of electronic systems. It publishes innovative work documenting significant research and development advances on the specification, design, analysis, simulation, testing, and evaluation of electronic systems, emphasizing a computer science/engineering orientation. Both theoretical analysis and practical solutions are welcome.