Efficient and lightweight in-memory computing architecture for hardware security

IF 3.4 3区 计算机科学 Q1 COMPUTER SCIENCE, THEORY & METHODS
Hala Ajmi , Fakhreddine Zayer , Amira Hadj Fredj, Hamdi Belgacem, Baker Mohammad, Naoufel Werghi, Jorge Dias
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Abstract

This paper introduces an innovative solution for improving the efficiency and speed of the Advanced Encryption Standard (AES) based cryptographic algorithm. The approach leverages in-memory computing (IMC) and is versatile for application across a broad spectrum of IoT applications, including robotic autonomous vehicles and various other scenarios. To achieve this goal, memristor (MR) designs are proposed to emulate the arithmetic operations required for different phases of the AES algorithm, enabling efficient in-memory processing. The key contributions of this work include; 1) The development of a 4 bit-MR state element for implementing different arithmetic operations in an AES hardware prototype; 2) The creation of a pipeline AES design for massive parallelism and MR integration compatibility; and 3) The hardware implementation of the AES-IMC based architecture using the MR emulator. The results show that AES-IMC performs better than existing architectures in terms of higher throughput and energy efficiency. Compared to conventional AES hardware, AES-IMC achieves a 30% power enhancement with comparable throughput. Additionally, when compared to state-of-the-art AES-based NVM engines, AES-IMC demonstrates comparable power dissipation and a 62% increase in throughput. The IMC architecture enables cost-effective real-time deployment of AES, leading to high-performance computing. By leveraging the power of in-memory computing, this system is able to provide improved computational efficiency and faster processing speeds, making it a promising solution for a wide range of applications in the field of autonomous driving and robotics. The potential benefits of this system include improved safety and security of unmanned devices, as well as enhanced performance and cost-effectiveness in a variety of computing environments.

面向硬件安全的高效轻量级内存计算架构
本文介绍了一种创新解决方案,用于提高基于高级加密标准(AES)的加密算法的效率和速度。该方法利用内存计算(IMC),适用于广泛的物联网应用,包括机器人自动驾驶汽车和其他各种场景。为了实现这一目标,我们提出了忆阻器(MR)设计,以模拟 AES 算法不同阶段所需的算术运算,从而实现高效的内存处理。这项工作的主要贡献包括:1)开发了用于在 AES 硬件原型中实现不同算术运算的 4 位 MR 状态元素;2)创建了用于大规模并行性和 MR 集成兼容性的流水线 AES 设计;3)使用 MR 仿真器实现了基于 AES-IMC 架构的硬件实施。结果表明,就更高的吞吐量和能效而言,AES-IMC 的性能优于现有架构。与传统的 AES 硬件相比,AES-IMC 在吞吐量相当的情况下提高了 30% 的功耗。此外,与最先进的基于 AES 的 NVM 引擎相比,AES-IMC 的功耗相当,吞吐量提高了 62%。IMC 架构实现了具有成本效益的 AES 实时部署,带来了高性能计算。通过利用内存计算的强大功能,该系统能够提供更高的计算效率和更快的处理速度,使其成为自动驾驶和机器人领域各种应用的理想解决方案。该系统的潜在优势包括提高无人驾驶设备的安全性,以及在各种计算环境中提高性能和成本效益。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
Journal of Parallel and Distributed Computing
Journal of Parallel and Distributed Computing 工程技术-计算机:理论方法
CiteScore
10.30
自引率
2.60%
发文量
172
审稿时长
12 months
期刊介绍: This international journal is directed to researchers, engineers, educators, managers, programmers, and users of computers who have particular interests in parallel processing and/or distributed computing. The Journal of Parallel and Distributed Computing publishes original research papers and timely review articles on the theory, design, evaluation, and use of parallel and/or distributed computing systems. The journal also features special issues on these topics; again covering the full range from the design to the use of our targeted systems.
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