DIR: Dynamic Request Interleaving for Improving the Read Performance of Aged Solid-State Drives

IF 1.2 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Shi-Qiang Nie, Chi Zhang, Wei-Guo Wu
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引用次数: 0

Abstract

Triple-level cell (TLC) NAND flash is increasingly adopted to build solid-state drives (SSDs) for modern computer systems. While TLC NAND flash effectively improves storage density, it faces severe reliability issues; in particular, the pages exhibit different raw bit error rates (RBERs). Integrating strong low-density parity-check (LDPC) code helps to improve reliability but suffers from prolonged and proportional read latency due to multiple read retries for worse pages. The straightforward idea is that dispersing page-size data across several pages in different types can achieve a lower average RBER and reduce the read latency. However, directly implementing this simple idea into flash translation layer (FTL) induces the read amplification issue as one logic page residing in more than one physical page brings several read operations. In this paper, we propose the Dynamic Request Interleaving (DIR) technology for improving the performance of TLC NAND flash-based SSDs, in particular, the aged ones with large RBERs. DIR exploits the observation that the latency of an I/O request is determined, without considering the queuing time, by the access of the slowest device page, i.e., the page that has the highest RBER. By grouping consecutive logical pages that have high locality and interleaving their encoded data in different types of device pages that have different RBERs, DIR effectively reduces the number of read retries for LDPC with limited read amplification. To meet the requirement of allocating hybrid page types for interleaved data, we also design a page-interleaving friendly page allocation scheme, which splits all the planes into multi-plane regions for storing the interleaved data and single-plane regions for storing the normal data. The pages in the multi-plane region can be read/written in parallel by the proposed multi-plane command and avoid the read amplification issue. Based on the DIR scheme and the proposed page allocation scheme, we build DIR-enable FTL, which integrates the proposed schemes into the FTL with some modifications. Our experimental results show that adopting DIR in aged SSDs exploits nearly 33% locality from I/O requests and, on average, reduces 43% read latency over conventional aged SSDs.

DIR:动态请求交错提高老化固态硬盘的读取性能
现代计算机系统越来越多地采用三层单元(TLC)NAND 闪存来制造固态硬盘(SSD)。虽然 TLC NAND 闪存能有效提高存储密度,但却面临着严重的可靠性问题,尤其是页面显示出不同的原始比特错误率(RBER)。集成强低密度奇偶校验(LDPC)码有助于提高可靠性,但由于对较差页面进行多次读取重试,会导致读取延迟时间延长,并与读取延迟时间成正比。直截了当的想法是,将页面大小的数据分散到不同类型的多个页面中,可以实现较低的平均 RBER 值,并减少读取延迟。然而,直接在闪存转换层(FTL)中实现这一简单想法会导致读取放大问题,因为一个逻辑页驻留在多个物理页中,会带来多个读取操作。在本文中,我们提出了动态请求交错(DIR)技术,以提高基于 TLC NAND 闪存的固态硬盘的性能,尤其是具有较大 RBER 的老式固态硬盘。DIR 利用了一个观察结果,即在不考虑排队时间的情况下,I/O 请求的延迟取决于对最慢设备页面(即 RBER 最高的页面)的访问。通过将具有高定位性的连续逻辑页分组,并将其编码数据交错在具有不同 RBER 的不同类型设备页中,DIR 可以有效减少具有有限读取放大功能的 LDPC 的读取重试次数。为了满足为交错数据分配混合页面类型的要求,我们还设计了一种页面交错友好型页面分配方案,该方案将所有平面划分为多平面区域和单平面区域,前者用于存储交错数据,后者用于存储正常数据。多平面区域中的页面可以通过拟议的多平面指令并行读/写,避免了读放大问题。在 DIR 方案和建议的页面分配方案的基础上,我们构建了 DIR-enable FTL,将建议的方案进行一些修改后集成到 FTL 中。我们的实验结果表明,在老化的固态硬盘中采用 DIR 可以从 I/O 请求中利用近 33% 的本地性,与传统的老化固态硬盘相比,平均可减少 43% 的读取延迟。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
Journal of Computer Science and Technology
Journal of Computer Science and Technology 工程技术-计算机:软件工程
CiteScore
4.00
自引率
0.00%
发文量
2255
审稿时长
9.8 months
期刊介绍: Journal of Computer Science and Technology (JCST), the first English language journal in the computer field published in China, is an international forum for scientists and engineers involved in all aspects of computer science and technology to publish high quality and refereed papers. Papers reporting original research and innovative applications from all parts of the world are welcome. Papers for publication in the journal are selected through rigorous peer review, to ensure originality, timeliness, relevance, and readability. While the journal emphasizes the publication of previously unpublished materials, selected conference papers with exceptional merit that require wider exposure are, at the discretion of the editors, also published, provided they meet the journal''s peer review standards. The journal also seeks clearly written survey and review articles from experts in the field, to promote insightful understanding of the state-of-the-art and technology trends. Topics covered by Journal of Computer Science and Technology include but are not limited to: -Computer Architecture and Systems -Artificial Intelligence and Pattern Recognition -Computer Networks and Distributed Computing -Computer Graphics and Multimedia -Software Systems -Data Management and Data Mining -Theory and Algorithms -Emerging Areas
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