Enlarging the Time Budget for Neural Network Based Predictors for Access Interval Prediction

Abstract

Embedded systems implemented on a single chip commonly contain several Processing Elements (PEs). To optimize both area and energy efficiency, these individual PEs are often linked to the same Tightly Coupled Memory (TCM). Nonetheless, the advantage of memory sharing is offset by potential conflicts. Recently introduced systems with offline conflict detection and memory arbitration avoid the performance degradation of online arbiters. Access Interval Prediction (AIP) is exploited to detect the conflicts offline by forecasting the time interval between two memory accesses. In this context, neural network models for time-series prediction are the State-of-the-Art AIP units. However, the influence of the latency of these neural network predictors on the accuracy of the AIP system has not been considered yet. Our analysis shows a significant degradation of the system accuracy by the predictor latency. To enlarge the time budget for calculation, we introduce a novel neural network AIP predictor that predicts the next-but-one memory access. Further, we present an advanced system model that integrates two independent next-but-one predictors. By combining multiple predictors, we can maintain the high accuracy of the AIP system even for implementations that exhibit high latency. For example, our system model demonstrates a 2.59 times higher accuracy compared to the State-of-the-Art AIP with neural networks when executing the models with a latency of 5 cycles.