Hardware security and reliability verification based on fault propagation model

Xige Zhang, Jiacheng Zhu, Jun Ma, Lixiang Shen, Jiahui Zhou, Dejun Mu
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引用次数: 0

Abstract

Large scale integrate circuits is facing serious threat such as design vulnerabilities, side channels, and hardware Trojans. Traditional functional verification method is difficult to ensure high test coverage, and it is also difficult to detect security vulnerabilities such as side channels and stealthy hardware Trojans. Formal verification methods focus on the equivalence and functional correctness of design, and are difficult to meet security and reliability verification needs. The present work proposes a hardware security and reliability verification method from formal model. The present method can develop formal models for describing the security and reliability behaviour of hardware designs. It can detect potential security vulnerabilities in hardware designs. Experimental results show that the verification method is effective in detecting sensitive information leakage and modification caused by side channels and hardware Trojans.
基于故障传播模型的硬件安全性和可靠性验证
大规模集成电路正面临着设计漏洞、侧信道和硬件木马等严重威胁。传统的功能验证方法很难确保高测试覆盖率,也很难检测到安全漏洞,如侧信道和隐蔽的硬件木马。形式化验证方法侧重于设计的等价性和功能正确性,难以满足安全性和可靠性验证的需求。本研究提出了一种从形式模型出发的硬件安全性和可靠性验证方法。本方法可开发描述硬件设计安全性和可靠性行为的形式化模型。它可以检测硬件设计中潜在的安全漏洞。实验结果表明,该验证方法能有效检测由侧信道和硬件木马引起的敏感信息泄漏和修改。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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