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Enhance Speed Low Area FPGA Design Using S-Box GF and Pipeline Approach on Logic for AES

Q3 Engineering
Mathematical Modelling of Engineering Problems Pub Date : 2024-03-28 DOI:10.18280/mmep.110322
K. J. Lakshmi, G. Sreenivasulu
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使用 S-Box GF 和流水线方法为 AES 进行高速、低面积 FPGA 设计
本文章由计算机程序翻译，如有差异，请以英文原文为准。
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来源期刊
Mathematical Modelling of Engineering Problems
Mathematical Modelling of Engineering Problems Engineering-Engineering (miscellaneous)
CiteScore
1.50
自引率
0.00%
发文量
146
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