Incremental Concolic Testing of Register-Transfer Level Designs

IF 2.2 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Hasini Witharana, Aruna Jayasena, Prabhat Mishra
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引用次数: 0

Abstract

Concolic testing is a scalable solution for automated generation of directed tests for validation of hardware designs. Unfortunately, concolic testing fails to cover complex corner cases such as hard-to-activate branches. In this paper, we propose an incremental concolic testing technique to cover hard-to-activate branches in register-transfer level (RTL) models. We show that a complex branch condition can be viewed as a sequence of easy-to-activate events. We map the branch coverage problem to the coverage of a sequence of events. We propose an efficient algorithm to cover the sequence of events using concolic testing. Specifically, the test generated to activate the current event is used as the starting point to activate the next event in the sequence. Experimental results demonstrate that our approach can be used to generate directed tests to cover complex corner cases in RTL models while state-of-the-art methods fail to activate them.
寄存器传输级设计的增量协整测试
协程测试是一种可扩展的解决方案,用于自动生成定向测试,以验证硬件设计。遗憾的是,协程测试无法覆盖复杂的角情况,如难以激活的分支。在本文中,我们提出了一种增量协程测试技术,以覆盖寄存器传输层(RTL)模型中难以激活的分支。我们表明,复杂的分支条件可被视为一系列易于激活的事件。我们将分支覆盖问题映射为事件序列的覆盖问题。我们提出了一种使用协程测试来覆盖事件序列的高效算法。具体来说,为激活当前事件而生成的测试被用作激活序列中下一个事件的起点。实验结果表明,我们的方法可用于生成定向测试,以覆盖 RTL 模型中的复杂角情况,而最先进的方法却无法激活这些角情况。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
ACM Transactions on Design Automation of Electronic Systems
ACM Transactions on Design Automation of Electronic Systems 工程技术-计算机:软件工程
CiteScore
3.20
自引率
7.10%
发文量
105
审稿时长
3 months
期刊介绍: TODAES is a premier ACM journal in design and automation of electronic systems. It publishes innovative work documenting significant research and development advances on the specification, design, analysis, simulation, testing, and evaluation of electronic systems, emphasizing a computer science/engineering orientation. Both theoretical analysis and practical solutions are welcome.
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